Patents by Inventor Nitin Deshpande
Nitin Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190148268Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Rajendra C. DIAS, Edvin CETEGEN, Lars D. SKOGLUND
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Patent number: 10256198Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: GrantFiled: March 23, 2017Date of Patent: April 9, 2019Assignee: INTEL CORPORATIONInventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
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Publication number: 20190103385Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: OMKAR KARHADE, ROBERT L. SANKMAN, NITIN A. DESHPANDE, MITUL MODI, THOMAS J. DE BONIS, ROBERT M. NICKERSON, ZHIMIN WAN, HAIFA HARIRI, SRI CHAITRA J. CHAVALI, NAZMIYE ACIKGOZ AKBAY, FADI Y. HAFEZ, CHRISTOPHER L. RUMER
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Publication number: 20190104610Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Robert Nickerson, Nitin Deshpande, Omkar Karhade, Thomas De Bonis
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Patent number: 10229882Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: GrantFiled: August 3, 2017Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Nitin A. Deshpande, Omkar G. Karhade
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Patent number: 10192810Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.Type: GrantFiled: June 28, 2013Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund
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Publication number: 20190006342Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermal structure is physically and thermally coupled to the upper surface of the first semiconductor package and to the lower surface of the second semiconductor package. The thermal structure has opposed first and second surfaces and includes a first adhesive layer disposed across the first surface and a second adhesive layer disposed across the second surface. The first adhesive layer physically and thermally couples the thermal structure to the lower surface of the second semiconductor package. The second adhesive layer physically and thermally couples the thermal structure to the upper surface of the first semiconductor package.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: OMKAR KARHADE, NITIN DESHPANDE
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Publication number: 20190006319Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: OMKAR KARHADE, CHRISTOPHER L. RUMER, NITIN DESHPANDE, ROBERT M. NICKERSON
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Publication number: 20180358296Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.Type: ApplicationFiled: December 22, 2015Publication date: December 13, 2018Inventors: Eric J. LI, Nitin DESHPANDE, Shawna M. LIFF, Omkar KARHADE, Amram EITAN, Timothy A. GOSSELIN
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Publication number: 20180277492Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: ApplicationFiled: March 23, 2017Publication date: September 27, 2018Applicant: INTEL CORPORATIONInventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
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Patent number: 10068852Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2017Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Publication number: 20180190510Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: ApplicationFiled: February 19, 2018Publication date: July 5, 2018Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
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Patent number: 9991243Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.Type: GrantFiled: February 20, 2017Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
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Patent number: 9941246Abstract: An electronic assembly that includes a first electronic device. The first electronic device includes a cavity that extends into a back side of the first electronic device. The electronic assembly further includes a second electronic device. The second electronic device is mounted to the first electronic device within the cavity in the first electronic device. In some example forms of the electronic assembly, the first electronic device and the second electronic device are each a die. It should be noted that other forms of the electronic assembly are contemplated where only one of the first electronic device and the second electronic device is a die. In some forms of the electronic assembly, the second electronic device is soldered to the first electronic device.Type: GrantFiled: July 2, 2014Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Nitin Deshpande, Ravi V. Mahajan
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Patent number: 9899238Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: GrantFiled: December 18, 2014Date of Patent: February 20, 2018Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
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Patent number: 9842832Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: GrantFiled: June 15, 2016Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
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Publication number: 20170330835Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Applicant: INTEL CORPORATIONInventors: Nitin A. Deshpande, Omkar G. Karhade
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Publication number: 20170323874Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.Type: ApplicationFiled: February 20, 2017Publication date: November 9, 2017Inventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
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Publication number: 20170301625Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 28, 2017Publication date: October 19, 2017Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Patent number: 9795038Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.Type: GrantFiled: September 25, 2014Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande, Nachiket Raravikar