Patents by Inventor Nitin Deshpande
Nitin Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170290155Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 20, 2017Publication date: October 5, 2017Inventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
-
Patent number: 9754890Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: GrantFiled: February 26, 2014Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Nitin A. Deshpande, Omkar G. Karhade
-
Patent number: 9741692Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.Type: GrantFiled: September 15, 2014Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh
-
Patent number: 9716067Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: GrantFiled: January 22, 2016Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
-
Patent number: 9713255Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.Type: GrantFiled: February 19, 2014Date of Patent: July 18, 2017Assignee: INTEL CORPORATIONInventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
-
Publication number: 20170200621Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.Type: ApplicationFiled: March 24, 2017Publication date: July 13, 2017Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, JR., Aditya Sundoctor VAIDYA, Nachiket R. RARAVIKAR, Eric J. LI
-
Patent number: 9685388Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: GrantFiled: October 18, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Patent number: 9685421Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.Type: GrantFiled: June 1, 2015Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
-
Patent number: 9659899Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.Type: GrantFiled: July 10, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
-
Patent number: 9607964Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.Type: GrantFiled: March 28, 2014Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Jr., Aditya Sundoctor Vaidya, Nachiket R. Raravikar, Eric J. Li
-
Patent number: 9583470Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.Type: GrantFiled: December 19, 2013Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande
-
Patent number: 9576942Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.Type: GrantFiled: December 18, 2015Date of Patent: February 21, 2017Assignee: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
-
Publication number: 20170040238Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Applicant: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Publication number: 20160343666Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: ApplicationFiled: February 26, 2014Publication date: November 24, 2016Applicant: INTEL CORPORATIONInventors: Nitin A. Deshpande, Omkar G. Karhade
-
Patent number: 9502368Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: GrantFiled: December 16, 2014Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Publication number: 20160300824Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: ApplicationFiled: June 15, 2016Publication date: October 13, 2016Applicant: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
-
Publication number: 20160268231Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.Type: ApplicationFiled: September 15, 2014Publication date: September 15, 2016Applicant: INTEL CORPORATIONInventors: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh
-
Publication number: 20160260688Abstract: An electronic assembly that includes a first electronic device. The first electronic device includes a cavity that extends into a back side of the first electronic device. The electronic assembly further includes a second electronic device. The second electronic device is mounted to the first electronic device within the cavity in the first electronic device. In some example forms of the electronic assembly, the first electronic device and the second electronic device are each a die. It should be noted that other forms of the electronic assembly are contemplated where only one of the first electronic device and the second electronic device is a die. In some forms of the electronic assembly, the second electronic device is soldered to the first electronic device.Type: ApplicationFiled: July 2, 2014Publication date: September 8, 2016Inventors: Nitin Deshpande, Ravi V. Mahajan
-
Patent number: 9397071Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.Type: GrantFiled: December 11, 2013Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
-
Publication number: 20160181218Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita