Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047001
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 8, 2024
    Applicant: Kioxia Corporation
    Inventor: Noboru SHIBATA
  • Patent number: 11874194
    Abstract: A vibration processing apparatus (10) includes: an acquisition unit (110) that reads, from a vibration information storage unit (112), information needed for detecting an abnormality in a belt conveyor (20), the information being, for example, first detection data indicating a result of detecting a vibration at a first point of the belt conveyor (20), and second detection data indicating a result of detecting a vibration at a second point on a downstream side of the first point of the belt conveyor (20); and a determination unit (120) that determines that an abnormality occurs in the belt conveyor with a necessary condition or a necessary and sufficient condition that a result of comparing the first detection data and the second detection data satisfies a first reference.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 16, 2024
    Assignee: NEC CORPORATION
    Inventors: Yasuharu Onishi, Yasuyuki Fukuta, Sae Watanabe, Noboru Tashiro, Michio Shibata
  • Publication number: 20240005988
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: September 14, 2023
    Publication date: January 4, 2024
    Applicant: Kioxia Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20230410899
    Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 21, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Patent number: 11837294
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: December 5, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Hironori Uchikawa
  • Patent number: 11830559
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Noboru Shibata
  • Patent number: 11763883
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 11756611
    Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Publication number: 20230282276
    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Applicant: Kioxia Corporation
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Publication number: 20230260577
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 17, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Jun NAKAI, Noboru SHIBATA
  • Publication number: 20230253029
    Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.
    Type: Application
    Filed: June 16, 2022
    Publication date: August 10, 2023
    Applicant: Kioxia Corporation
    Inventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Yusuke ARAYASHIKI, Motohiko FUJIMATSU, Kyosuke SANO, Noboru SHIBATA
  • Publication number: 20230253054
    Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicant: Kioxia Corporation
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
  • Publication number: 20230245697
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Application
    Filed: April 6, 2023
    Publication date: August 3, 2023
    Applicant: Kioxia Corporation
    Inventor: Noboru SHIBATA
  • Publication number: 20230238059
    Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
    Type: Application
    Filed: April 4, 2023
    Publication date: July 27, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20230206998
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 29, 2023
    Applicant: Kioxia Corporation
    Inventors: Noboru SHIBATA, Yasuyuki MATSUDA
  • Publication number: 20230207000
    Abstract: According to one embodiment, a memory device is configured to execute an efficient read operation is provided. The memory device includes a plurality of memory cells, a word line, and a controller. Each of the memory cells stores first to fifth bit data based on the threshold voltage. The memory cells store a first page to a fifth page respectively corresponding to the first bit data to the fifth bit data. A word line is coupled to the memory cells. A controller executes a read operation for reading data from the memory cells by applying a read voltage to the word line. Numbers of times the controller applies read voltages different from one another to the word line in read operations for the first page to the fifth page are 7, 6, 6, 6, and 6, respectively.
    Type: Application
    Filed: August 10, 2022
    Publication date: June 29, 2023
    Applicant: Kioxia Corporation
    Inventors: Mitsuaki HONMA, Noboru SHIBATA
  • Patent number: 11688458
    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: June 27, 2023
    Assignee: Kioxia Corporation
    Inventors: Noboru Shibata, Tokumasa Hara
  • Patent number: 11664077
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • Patent number: 11657879
    Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: May 23, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Hironori Uchikawa, Taira Shibuya
  • Patent number: 11651817
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventor: Noboru Shibata