Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device capable of reducing chip size
    Patent number: 10783971
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20200279608
    Abstract: According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n?1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n?1) layers of select gate layers include first to (2×(n?1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n?1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k?2)th select gates. The nth string unit is selected by the nth to (2×(n?1))th select gates.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Noboru SHIBATA, Kazuaki ISOBE
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    Publication number: 20200273524
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL
    Publication number: 20200251165
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Application
    Filed: April 24, 2020
    Publication date: August 6, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA
    Publication number: 20200234779
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data n the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • SEMICONDUCTOR MEMORY WITH DIFFERENT THRESHOLD VOLTAGES OF MEMORY CELLS
    Publication number: 20200227122
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA
  • Semiconductor memory device and memory system
    Patent number: 10714170
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tokumasa Hara
  • SEMICONDUCTOR MEMORY
    Publication number: 20200211655
    Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Applicant: KIOXIA CORPORATION
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 10699781
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k?n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i?k) threshold voltage.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20200194088
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Hiroshi MAEJIMA, Noboru SHIBATA
  • Nonvolatile semiconductor memory device which performs improved erase operation
    Patent number: 10685715
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • Semiconductor memory device
    Patent number: 10679700
    Abstract: According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n?1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n?1) layers of select gate layers include first to (2×(n?1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n?1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k?2)th select gates. The nth string unit is selected by the nth to (2×(n?1))th select gates.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Kazuaki Isobe
  • Semiconductor memory device
    Patent number: 10672487
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Koji Hosono, Tadashi Yasufuku, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20200143877
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Semiconductor memory device and memory system
    Patent number: 10643693
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
  • Semiconductor memory device for storing multivalued data
    Patent number: 10636502
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor memory device
    Patent number: 10614900
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Maejima, Noboru Shibata
  • Semiconductor memory with different threshold voltages of memory cells
    Patent number: 10607707
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Noboru Shibata, Hironori Uchikawa
  • SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
    Publication number: 20200090753
    Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Weihan WANG, Takahiro SHIMIZU, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20200066349
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Hiroshi SUKEGAWA