Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining l0 the first memory cells in the bit line direction.

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.