Patents by Inventor Noboru Shibata
Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220084609Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.Type: ApplicationFiled: March 15, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Motohiko FUJIMATSU, Noboru SHIBATA
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Patent number: 11270765Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.Type: GrantFiled: January 21, 2021Date of Patent: March 8, 2022Assignee: Toshiba Memory CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 11264108Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.Type: GrantFiled: November 23, 2020Date of Patent: March 1, 2022Assignee: KIOXIA CORPORATIONInventors: Noboru Shibata, Tomoharu Tanaka
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Patent number: 11264090Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.Type: GrantFiled: September 8, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 11238925Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.Type: GrantFiled: December 30, 2020Date of Patent: February 1, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Noboru Shibata, Tokumasa Hara
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Patent number: 11238924Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.Type: GrantFiled: September 10, 2020Date of Patent: February 1, 2022Assignee: Kioxia CorporationInventors: Tokumasa Hara, Noboru Shibata
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Publication number: 20210398598Abstract: A semiconductor memory device according to an embodiment includes first memory cells, second memory cells, and a controller. A threshold voltage of each of the first memory cells and the second memory cells is included in one of first through sixteenth state. 8-bit data that includes a first through eighth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. The controller is configured to: apply in parallel a plurality of types of read voltages to each of the first memory cells and the second memory cells and externally output data confirmed based on first data read from the first memory cells and second data read from the second memory cells.Type: ApplicationFiled: June 16, 2021Publication date: December 23, 2021Applicant: Kioxia CorporationInventors: Taira SHIBUYA, Noboru SHIBATA, Hironori UCHIKAWA
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Patent number: 11183243Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.Type: GrantFiled: November 22, 2019Date of Patent: November 23, 2021Assignee: KIOXIA CORPORATIONInventors: Weihan Wang, Takahiro Shimizu, Noboru Shibata
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Patent number: 11176999Abstract: According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n?1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n?1) layers of select gate layers include first to (2×(n?1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n?1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k?2)th select gates. The nth string unit is selected by the nth to (2×(n?1))th select gates.Type: GrantFiled: January 6, 2021Date of Patent: November 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Noboru Shibata, Kazuaki Isobe
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Publication number: 20210343336Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventor: Noboru SHIBATA
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Publication number: 20210312996Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.Type: ApplicationFiled: June 16, 2021Publication date: October 7, 2021Applicant: Toshiba Memory CorporationInventor: Noboru SHIBATA
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Publication number: 20210304821Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Applicant: Toshiba Memory CorporationInventors: Jun NAKAI, Noboru SHIBATA
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Publication number: 20210264990Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.Type: ApplicationFiled: April 29, 2021Publication date: August 26, 2021Applicant: Kioxia CorporationInventors: Noboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
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Patent number: 11074969Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.Type: GrantFiled: October 15, 2020Date of Patent: July 27, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Noboru Shibata
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Patent number: 11062777Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.Type: GrantFiled: May 11, 2020Date of Patent: July 13, 2021Assignee: Toshiba Memory CorporationInventors: Jun Nakai, Noboru Shibata
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Patent number: 11056202Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k(k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.Type: GrantFiled: October 3, 2019Date of Patent: July 6, 2021Assignee: Toshiba Memory CorporationInventor: Noboru Shibata
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Publication number: 20210174876Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Noboru SHIBATA, Hiroshi SUKEGAWA
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Publication number: 20210166755Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.Type: ApplicationFiled: January 21, 2021Publication date: June 3, 2021Applicant: Toshiba Memory CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Publication number: 20210158867Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.Type: ApplicationFiled: September 10, 2020Publication date: May 27, 2021Applicant: Kioxia CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Publication number: 20210151099Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.Type: ApplicationFiled: January 26, 2021Publication date: May 20, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Noboru SHIBATA, Yasuyuki MATSUDA