Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    Publication number: 20170330629
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Application
    Filed: August 1, 2017
    Publication date: November 16, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Jun NAKAI, Noboru SHIBATA
  • Memory system
    Patent number: 9799406
    Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Manabu Sato, Daiki Watanabe, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Naomi Takeda, Noboru Shibata, Takahiro Shimizu
  • Semiconductor memory device
    Patent number: 9761307
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • Nonvolatile semiconductor memory device which performs improved erase operation
    Patent number: 9754672
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Nakai, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170236595
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
    Type: Application
    Filed: January 12, 2017
    Publication date: August 17, 2017
    Inventors: Hiroshi MAEJIMA, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE
    Publication number: 20170186490
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 29, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki ISOBE, Noboru SHIBATA, Toshiki HISADA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170178739
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Application
    Filed: August 10, 2016
    Publication date: June 22, 2017
    Inventors: Hiroshi MAEJIMA, Koji HOSONO, Tadashi YASUFUKU, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL
    Publication number: 20170178721
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20170154679
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru SHIBATA, Hiroshi SUKEGAWA
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME
    Publication number: 20170148524
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Noboru SHIBATA
  • Semiconductor memory device capable of reducing chip size
    Patent number: 9633736
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 9627048
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 18, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor storage device
    Patent number: 9613720
    Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouichirou Yamaguchi, Makoto Miakashi, Hitoshi Shiga, Noboru Shibata
  • Semiconductor memory system including a plurality of semiconductor memory devices
    Patent number: 9601206
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: March 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • Semiconductor memory device capable of shortening erase time
    Patent number: 9595344
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA
    Publication number: 20170053706
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Application
    Filed: August 30, 2016
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • Semiconductor memory device including a NAND string
    Patent number: 9558828
    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Noboru Shibata
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    Publication number: 20160365153
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun NAKAI, Noboru SHIBATA
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20160322369
    Abstract: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: Noboru SHIBATA, Hiroshi SUKEGAWA
  • HIGH-SPEED READABLE SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20160322111
    Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Noboru SHIBATA