Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20200066349
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Hiroshi SUKEGAWA
  • Semiconductor memory device and memory system
    Patent number: 10566051
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit and a second bit is received from an external controller, the received first data is written to the first memory cell. When second data including a third bit and a fourth bit is received after the first data is received from the controller, the first data is read from the first memory cell and the 3-bit data is written to the first memory cell based on 1-bit of the read first data and the received second data.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tokumasa Hara
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20200051622
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND WRITE METHOD
    Publication number: 20200043549
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Yasuyuki MATSUDA
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME
    Publication number: 20200035311
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Noboru SHIBATA
  • Semiconductor storage device and memory system
    Patent number: 10515700
    Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: December 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Weihan Wang, Takahiro Shimizu, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA
    Publication number: 20190362797
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190362782
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL
    Publication number: 20190362781
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor memory device and memory system
    Patent number: 10490269
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
  • NONVOLATILE MEMORY AND WRITING METHOD
    Publication number: 20190355412
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Semiconductor memory system including a plurality of semiconductor memory devices
    Patent number: 10482970
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190325973
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Hiroshi MAEJIMA, Koji HOSONO, Tadashi YASUFUKU, Noboru SHIBATA
  • Semiconductor memory device capable of shortening erase time
    Patent number: 10446247
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 10431297
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Nonvolatile memory and writing method
    Patent number: 10431298
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Semiconductor memory device for storing multivalued data
    Patent number: 10418117
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor memory device
    Patent number: 10418096
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE
    Publication number: 20190279721
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190267108
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Hiroshi MAEJIMA, Noboru SHIBATA