Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two-level and multi-level data storage semiconductor memory device
    Patent number: 10049749
    Abstract: A semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k?1 levels (k?n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180226123
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Application
    Filed: March 30, 2018
    Publication date: August 9, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru SHIBATA
  • Semiconductor memory device
    Patent number: 10037813
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 31, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Noboru Shibata
  • Semiconductor memory device capable of shortening erase time
    Patent number: 10037812
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • High-speed readable semiconductor storage device
    Patent number: 10026484
    Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE
    Publication number: 20180190359
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 5, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Semiconductor memory device
    Patent number: 10002671
    Abstract: A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 19, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Takahiro Shimizu, Noboru Shibata, Hiroshi Maejima
  • SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20180151229
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Application
    Filed: January 26, 2018
    Publication date: May 31, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Hiroshi Sukegawa
  • Semiconductor memory device
    Patent number: 9984761
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Koji Hosono, Tadashi Yasufuku, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA
    Publication number: 20180122488
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Application
    Filed: December 18, 2017
    Publication date: May 3, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu Tanaka
  • Semiconductor memory device
    Patent number: 9953704
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL
    Publication number: 20180096723
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor memory device capable of reducing chip size
    Patent number: 9934861
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Semiconductor memory system including a plurality of semiconductor memory devices
    Patent number: 9928913
    Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Hiroshi Sukegawa
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180075912
    Abstract: A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Inventors: Takahiro SHIMIZU, Noboru SHIBATA, Hiroshi MAEJIMA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180061489
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Application
    Filed: August 15, 2017
    Publication date: March 1, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru SHIBATA
  • Semiconductor memory device for storing multivalued data
    Patent number: 9881681
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 9858992
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20170365335
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Application
    Filed: November 8, 2016
    Publication date: December 21, 2017
    Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
  • Memory system and writing method
    Patent number: 9830983
    Abstract: A nonvolatile memory device includes memory cells, bit lines, a word line, and a control unit performing a write operation in first and second stages. During the first stage, the control unit applies voltages to the word line and the bit lines based on first page of data to maintain threshold voltages for a first group of memory cells and shift the threshold voltages for a second group of memory cells above a first threshold. During the second stage, the control unit applies voltages to the word line and the bit lines based on second and third pages of data to shift the threshold voltages of memory cells in the first group to threshold voltages in one of first, second, and third threshold voltage ranges and the threshold voltages of memory cells in the second group to threshold voltages in one of fourth, fifth, sixth, and seventh threshold voltage ranges.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata