Patents by Inventor Noboru Shibata

Noboru Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
    Publication number: 20190267090
    Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.
    Type: Application
    Filed: October 18, 2018
    Publication date: August 29, 2019
    Inventors: Weihan WANG, Takahiro SHIMIZU, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY
    Publication number: 20190259458
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Application
    Filed: September 6, 2018
    Publication date: August 22, 2019
    Inventors: Noboru SHIBATA, Hironori UCHIKAWA
  • Semiconductor memory device
    Patent number: 10381096
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Koji Hosono, Tadashi Yasufuku, Noboru Shibata
  • Semiconductor memory device capable of reducing chip size
    Patent number: 10347341
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • NONVOLATILE MEMORY AND WRITING METHOD
    Publication number: 20190189201
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Semiconductor memory device
    Patent number: 10319450
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line, a word line, and a sense amplifier which is connected to the first bit line. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations. The sense amplifier applies a charging voltage to the first bit line during two of the seven verification operations, and does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190122734
    Abstract: According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n?1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n?1) layers of select gate layers include first to (2×(n?1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n?1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k?2)th select gates. The nth string unit is selected by the nth to (2×(n?1))th select gates.
    Type: Application
    Filed: July 30, 2018
    Publication date: April 25, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Kazuaki Isobe
  • Nonvolatile memory and writing method
    Patent number: 10255971
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL
    Publication number: 20190074057
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 7, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: NOBORU SHIBATA, Tomoharu Tanaka
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    Publication number: 20190074064
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20190043568
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Application
    Filed: October 10, 2018
    Publication date: February 7, 2019
    Inventors: Weihan WANG, Toshifumi HASHIMOTO, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA
    Publication number: 20190013082
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Application
    Filed: September 14, 2018
    Publication date: January 10, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • Nonvolatile semiconductor memory device which performs improved erase operation
    Patent number: 10157675
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Nakai, Noboru Shibata
  • Semiconductor memory device and memory system
    Patent number: 10121536
    Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Weihan Wang, Toshifumi Hashimoto, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180315486
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line, a word line, and a sense amplifier which is connected to the first bit line. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations. The sense amplifier applies a charging voltage to the first bit line during two of the seven verification operations, and does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 1, 2018
    Inventors: Hiroshi MAEJIMA, Noboru SHIBATA
  • SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME
    Publication number: 20180308557
    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Noboru SHIBATA
  • Semiconductor memory device for storing multivalued data
    Patent number: 10109358
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180301197
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Application
    Filed: May 23, 2018
    Publication date: October 18, 2018
    Inventors: Hiroshi MAEJIMA, Koji HOSONO, Tadashi YASUFUKU, Noboru SHIBATA
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 10096358
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20180240515
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit and a second bit is received from an external controller, the received first data is written to the first memory cell. When second data including a third bit and a fourth bit is received after the first data is received from the controller, the first data is read from the first memory cell and the 3-bit data is written to the first memory cell based on 1-bit of the read first data and the received second data.
    Type: Application
    Filed: September 12, 2017
    Publication date: August 23, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA