Patents by Inventor Nobuhiko Sato

Nobuhiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7642179
    Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: January 5, 2010
    Assignee: Canon Kabuhsiki Kaisha
    Inventors: Hajime Ikeda, Kazuya Notsu, Nobuhiko Sato, Shoji Nishida
  • Patent number: 7636993
    Abstract: A method for producing a piezoelectric film actuator is provided. This method includes the steps of preparing an intermediate transfer member having a porous layer formed thereon, with a vibrating plate and a piezoelectric layer being provided on the porous layer; bonding the vibrating plate to a nozzle substrate to form a composite structure; and separating the intermediate transfer member from the composite structure at the porous layer to transfer the vibrating plate and the piezoelectric layer to the nozzle substrate.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: December 29, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takehito Okabe, Nobuhiko Sato, Makoto Kurotobi, Kenichi Takeda, Toshihiro Ifuku
  • Publication number: 20090130782
    Abstract: A method is provided for manufacturing a semiconductor device that includes a multilayer wiring structure in which insulating layers and wiring layers each with a plurality of conductor lines are alternately stacked on each other. The method includes steps of forming a first wiring layer on a first insulating layer, detecting a defect in the first wiring layer on the first insulating layer, and determining whether or not the defect is to be irradiated with a focused ion beam, according to a detection result. If it is determined that the defect is to be irradiated, the defect is irradiated with a focused ion beam and then a second insulating layer is formed on the first wiring layer disposed on the first insulating layer. If it is determined that the defect is not to be irradiated with a focused ion beam, the second insulating layer is formed on the first wiring layer disposed on the first insulating layer without irradiating the defect.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 21, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Masatsugu Itahashi, Kouhei Hashimoto, Nobuhiko Sato, Seiichi Tamura, Hiroshi Yuzurihara
  • Publication number: 20090085196
    Abstract: This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
    Type: Application
    Filed: December 4, 2008
    Publication date: April 2, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazutaka Momoi, Nobuhiko Sato
  • Patent number: 7473617
    Abstract: This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: January 6, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutaka Momoi, Nobuhiko Sato
  • Publication number: 20080307622
    Abstract: A method for producing a piezoelectric film actuator is provided. This method includes the steps of preparing an intermediate transfer member having a porous layer formed thereon, with a vibrating plate and a piezoelectric layer being provided on the porous layer; bonding the vibrating plate to a nozzle substrate to form a composite structure; and separating the intermediate transfer member from the composite structure at the porous layer to transfer the vibrating plate and the piezoelectric layer to the nozzle substrate.
    Type: Application
    Filed: April 18, 2008
    Publication date: December 18, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takehito Okabe, Nobuhiko Sato, Makoto Kurotobi, Kenichi Takeda, Toshihiro Ifuku
  • Publication number: 20080298731
    Abstract: A hydrodynamic bearing device 30 comprises a sleeve 32 having a bearing hole 32d, a shaft 31, and a flange cover 33. The shaft 31 is disposed in the bearing hole 32d of the sleeve in a state of being capable of relative rotation, and has a large diameter flange portion 31b. The flange cover 33 is disposed opposite the bottom surface of the flange portion 31b. A bubble suppression portion 36, which is formed as a recess on the bottom surface of the shaft 31, communicates with the upper surface of the flange portion 31b through a communicating hole 31e in the flange portion 31b. This provides a hydrodynamic bearing device with which negative pressure is prevented from being generated in the bearing even when it is subjected to impact or vibration, and durability and reliability can be enhanced, as well as a spindle motor and a recording and reproducing apparatus equipped with this hydrodynamic bearing device.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Inventors: Toshifumi Hino, Nobuhiko Sato
  • Publication number: 20080298730
    Abstract: To provide a hydrodynamic bearing device with which the generation of negative pressure inside the bearing portion can be prevented, and durability and reliability can be increased, even when the hydrodynamic bearing device is subjected to impact or vibration, and to provide a spindle motor and a recording and reproducing apparatus equipped with this hydrodynamic bearing device. A hydrodynamic bearing device 30 comprises a sleeve 32, a shaft 31, and a flange cover 33. The sleeve has a bearing hole 32d and a communicating hole 32c which communicates between both end faces. The shaft 31 is disposed in a state of being capable of relative rotation in the bearing hole 32d of the sleeve, and has a main portion 31a, a flange 31b that is larger in diameter than the main portion 31a, and a communicating hole 31e that communicates with both end faces of the flange 31b. The flange cover 33 is disposed opposing to the lower face of the flange.
    Type: Application
    Filed: February 1, 2008
    Publication date: December 4, 2008
    Inventors: Toshifumi HINO, Nobuhiko SATO
  • Publication number: 20080263502
    Abstract: A method for generating mask pattern data of a photomask used to form microlenses divides a pattern formation surface of a mask pattern to be used for the photomask into a plurality of grid cells, acquires data which represents transmitted light distribution of the mask pattern to be used for the photomask, determines whether to place a shield on each of the plurality of grid cells by binarizing the plurality of grid cells in order of increasing or decreasing distance from a center of the pattern formation surface using an error diffusion method to acquire the transmitted light distribution, and generates mask pattern data which represents an arrangement of the shields based on results from the determining step.
    Type: Application
    Filed: March 14, 2008
    Publication date: October 23, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kyouhei Watanabe, Masaki Kurihara, Hitoshi Shindo, Nobuhiko Sato, Yasuhiro Sekine, Masataka Ito
  • Publication number: 20080218010
    Abstract: The present invention provides a motor that enables a lead of a coil to be appropriately led through holes, while allowing the lead of the coil to be fixed without contacting a wall surface of the hole in a base. Cuts 14b are formed in an insulating sheet or a printed circuit board 14; the cuts 14b extend substantially radially or spirally from a lead lead-out portion 14a as a center. Thus, even if an end of the lead 7a abuts against an area located outside the lead lead-out portion 14a, the abutting area and a nearby area located in the vicinity of the abutting area are pushed open along the cuts 14b extending from the lead lead-out portion 14a and guide the end of the lead 7a toward the lead lead-out portion 14a. The end of the lead 7a is thus appropriately guided into the lead lead-out portion 14a.
    Type: Application
    Filed: February 13, 2008
    Publication date: September 11, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshifumi Hino, Nobuhiko Sato
  • Publication number: 20080204929
    Abstract: An object of the present invention is to provide a method of manufacturing a fluid dynamic bearing device and a bearing part for a thrust bearing, both of which are applied to a flat and thin bearing part and are capable of preventing abrasion and scratching even if two parts make contact with each other. A fluid dynamic bearing mechanism 40 includes a shaft 1 functioning as an axis of rotational, a sleeve, a flange 3, a thrust plate 4, and a thrust bearing portion 22. The sleeve is disposed on the outer peripheral side of the shaft. The flange is disposed in the vicinity of the end portion of the shaft, and includes a bottom surface 3c perpendicular to a central axis direction of the shaft. A thrust receiver includes a front surface 4a opposed to the bottom surface. The thrust bearing portion is formed between the bottom surface and the front surface, and includes a plurality of thrust dynamic generation grooves 3a formed on the bottom surface.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 28, 2008
    Inventors: Shoji Masazuki, Toshifumi Hino, Kenichi Yano, Nobuhiko Sato
  • Publication number: 20080203450
    Abstract: A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 28, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Naruse, Takashi Okagawa, Ryuichi Mishima, Nobuhiko Sato, Hiroshi Yuzurihara
  • Publication number: 20070272944
    Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
    Type: Application
    Filed: February 28, 2007
    Publication date: November 29, 2007
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Kiyofumi Sakaguchi, Nobuhiko Sato, Hajime Ikeda, Shoji Nishida
  • Patent number: 7254428
    Abstract: Blood sugar levels are measured non-invasively based on temperature measurement. Non-invasively measured blood sugar level values obtained by a temperature measurement scheme are corrected by blood oxygen saturation and blood flow volume, thereby stabilizing the measurement data. A guide is provided for guiding an analyte to a measurement portion.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Ok-Kyung Cho, Yoon-Ok Kim, Nobuhiko Sato, Hiroshi Mitsumaki
  • Patent number: 7238973
    Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain induction porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: July 3, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Kiyofumi Sakaguchi, Nobuhiko Sato, Hajime Ikeda, Shoji Nishida
  • Publication number: 20070062814
    Abstract: A capillary array capable of being easily mounted on an electrophoresis apparatus without damaging the capillaries. The capillary array can include a plurality of capillaries that can be fixed via hollow electrodes on a load header in a matrix arrangement. The load header can be disposed on the electrophoresis apparatus. The capillary array can include a capillary frame onto which a capillary head and a detection portion can be detachably mounted. The structure allows the load header, the capillary head, the detection unit and other portions of the capillary array to be handled as a unit, thereby making it easier to mount the capillary array on the electrophoresis apparatus.
    Type: Application
    Filed: November 27, 2006
    Publication date: March 22, 2007
    Inventors: Takayasu Furukawa, Nobuhiko Sato, Syozo Kasai, Seiichi Ugai, Motohiro Yamazaki, Hiroyuki Tanaka, Yuki Nonaka, Yoshio Onodera, Noriyuki Shimoda
  • Patent number: 7164183
    Abstract: A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 16, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Nobuhiko Sato
  • Patent number: 7156971
    Abstract: A capillary array capable of being easily mounted on an electrophoresis apparatus without damaging the capillaries. The capillary array can include a plurality of capillaries that can be fixed via hollow electrodes on a load header in a matrix arrangement. The load header can be disposed on the electrophoresis apparatus. The capillary array can include a capillary frame onto which a capillary head and a detection portion can be detachably mounted. The structure allows the load header, the capillary head, the detection unit and other portions of the capillary array to be handled as a unit, thereby making it easier to mount the capillary array on the electrophoresis apparatus.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: January 2, 2007
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takayasu Furukawa, Nobuhiko Sato, Syozo Kasai, Seiichi Ugai, Motohiro Yamazaki, Hiroyuki Tanaka, Yuki Nonaka, Yoshio Onodera, Noriyuki Shimoda
  • Patent number: 7081970
    Abstract: An information processing apparatus includes an acquiring unit for acquiring information stored in a memory of a printing device connected through a bidirectional interface, and a selecting unit for selecting a printer driver corresponding to the information acquired by the acquiring unit from a plurality of printer drivers on the basis of the information.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: July 25, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Satoshi Nagata, Yoshifumi Okamoto, Tetsuya Morita, Akihiro Shimura, Shunya Mitsuhashi, Takanori Nishijima, Masaki Unishi
  • Publication number: 20060124961
    Abstract: A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 15, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kiyofumi Sakaguchi, Kazuya Notsu, Kazutaka Momoi, Nobuhiko Sato