Patents by Inventor Nobuhiko Sato

Nobuhiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shaver
    Patent number: 7055246
    Abstract: The present invention relates to the shaver capable of cutting deeply, provided with the outer blade having a plurality of the hair-guiding ports and the inner blade being adjacently located to the inner part of the outer blade and relatively moving against the said inner part, serving like an electric shaver of rotation or motion, which consists in going back and forth adjacently, wherein there is provided an escaping gap for taking hairs out in one part between the outer and inner blades, thus hooking the hairs guided into the gap, on the tip of the inner blade or pinching them inside the escaping gap and afterward, taking out the hairs and beards from the root of hairs and when the hairs move to the region without any escaping gap, they will be cut in the deep location.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: June 6, 2006
    Inventors: Teizoh Satoh, Nobuhiko Sato
  • Semiconductor member, manufacturing method thereof, and semiconductor device
    Publication number: 20060113635
    Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain induction porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 1, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Notsu, Kiyofumi Sakaguchi, Nobuhiko Sato, Hajime Ikeda, Shoji Nishida
  • Member and member manufacturing method
    Patent number: 7049624
    Abstract: A porous structure with high uniformity is provided even when evaluated at a high resolution (high evaluation standard) of several or several ten nm or less. By applying this porous structure to the manufacture of an SOI substrate, an SOI substrate which has an SOI layer with a small number of defects is provided. In a region at a depth of 5 to 10 nm from the surface of a porous Si layer, values of parameters such as porosity and the like which represent a porous structure are uniformed. The manufacture of an SOI substrate using this porous Si layer reduces recessed defects in an SOI layer.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: May 23, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hajime Ikeda, Nobuhiko Sato, Kiyofumi Sakaguchi
  • Optical measurement apparatus and blood sugar level measuring apparatus using the same
    Publication number: 20060094941
    Abstract: An apparatus for non-invasively measuring blood sugar levels based on temperature measurements. A blood sugar level non-invasively measured by a temperature measuring method is corrected by blood oxygen saturation and blood flow volume. Optical sensors detect scattered light, reflected light, and light exiting from a body surface after penetrating the skin, so that measurement data can be stabilized by taking into consideration the influence of the thickness of the skin on blood oxygen saturation.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Ok-Kyung Cho, Yoon-Ok Kim, Nobuhiko Sato, Hiroshi Mitsumaki
  • Electrochemical processing apparatus and method
    Publication number: 20060070884
    Abstract: A processing apparatus electrochemically processes part of a first surface of a member having the first surface and a second surface. The processing apparatus includes a support which supports the member to expose the first surface, a first electrode which is arranged to oppose a first portion of the first surface, a second electrode which is arranged to oppose a second portion of the first surface, a third electrode which applies a potential to the member from a second surface side, and a processing bath to fill a space defined by the first and second electrodes and the member with a processing liquid.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 6, 2006
    Inventors: Kazutaka Momoi, Kazutaka Yanaqita, Nobuhiko Sato
  • Inkjet head and method for manufacturing the same
    Publication number: 20060049135
    Abstract: A method for manufacturing an inkjet head includes providing a piezoelectric substrate having a porous structure, a diaphragm on the porous structure, and a piezoelectric substance layer on the diaphragm, and forming a cavity by etching out the porous structure from the piezoelectric substrate.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 9, 2006
    Applicant: Canon Kabushiki Kaisha
    Inventors: Takehito Okabe, Nobuhiko Sato, Makoto Kurotobi, Kenichi Takeda, Toshihiro Ifuku
  • Method for producing piezoelectric film actuator, and composite structure having piezoelectric layer
    Publication number: 20060049723
    Abstract: A method for producing a piezoelectric film actuator is provided. This method includes the steps of preparing an intermediate transfer member having a porous layer formed thereon, with a vibrating plate and a piezoelectric layer being provided on the porous layer; bonding the vibrating plate to a nozzle substrate to form a composite structure; and separating the intermediate transfer member from the composite structure at the porous layer to transfer the vibrating plate and the piezoelectric layer to the nozzle substrate.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 9, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takehito Okabe, Nobuhiko Sato, Makoto Kurotobi, Kenichi Takeda, Toshihiro Ifuku
  • Semiconductor device and method of manufacturing the same
    Publication number: 20060049487
    Abstract: A semiconductor device manufacturing method is disclosed. A semiconductor substrate having a separation region and a semiconductor region which covers the separation region entirely is prepared. One or a plurality of circuit elements are formed in the semiconductor region. The semiconductor substrate is split at the separation region.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 9, 2006
    Inventors: Nobuhiko Sato, Shigeru Kido, Kazutaka Momoi
  • Semiconductor member manufacturing method and semiconductor device manufacturing method
    Patent number: 7008701
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15?), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10?). This first substrate (10?) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: March 7, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Semiconductor substrate and manufacturing method for the same
    Publication number: 20060035447
    Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 16, 2006
    Inventors: Hajime Ikeda, Kazuya Notsu, Nobuhiko Sato, Shoji Nishida
  • Integrated circuit chip manufacturing method and semiconductor device
    Publication number: 20050280119
    Abstract: This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 22, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kazutaka Momoi, Nobuhiko Sato
  • SOI substrate and method of manufacturing the same
    Publication number: 20050196934
    Abstract: A SOI substrate manufacturing method includes steps of preparing a substrate having a non-porous semiconductor layer on a porous portion, and executing an oxidation process for the substrate to at least partially oxidize the porous portion and change it to a buried oxide layer.
    Type: Application
    Filed: February 11, 2005
    Publication date: September 8, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventors: Koichi Tazoe, Nobuhiko Sato
  • Blood sugar level measuring apparatus
    Publication number: 20050182311
    Abstract: Blood sugar levels are measured non-invasively based on temperature measurement. Non-invasively measured blood sugar level values obtained by a temperature measurement scheme are corrected by blood oxygen saturation and blood flow volume, thereby stabilizing the measurement data. A guide is provided for guiding an analyte to a measurement portion.
    Type: Application
    Filed: March 31, 2004
    Publication date: August 18, 2005
    Inventors: Ok-Kyung Cho, Yoon-Ok Kim, Nobuhiko Sato, Hiroshi Mitsumaki
  • Member which includes porous silicon region, and method of manufacturing member which contains silicon
    Publication number: 20050133865
    Abstract: A technique capable of forming a high-quality nonporous layer with little defects is provided. When an average pore size and pore density are defined as D (nm) and N (pores/cm2), respectively, a silicon wafer is anodized to satisfy 0<N?1.9×1012 and 0.235 nm?D<91 nm to form a porous silicon region in the region near the upper surface of the porous silicon region.
    Type: Application
    Filed: December 13, 2004
    Publication date: June 23, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hajime Ikeda, Kiyofumi Sakaguchi, Nobuhiko Sato
  • Cooperative system and method therefor
    Publication number: 20050038911
    Abstract: A cooperative system includes a plurality of information systems and a hub system connected to the plurality of systems. The hub system receives a message from a first information system, determines necessity of message conversion and a kind of conversion, converts the message to a form suitable for a second information system which is destination, only when message conversion is necessary, and transmits the message to a second information system. The hub system may determine whether flow control determining a flow and destination of a message received from the first information system based on a class of the message should be conducted, and conduct flow control only when it has been determined that flow control should be conducted.
    Type: Application
    Filed: September 22, 2004
    Publication date: February 17, 2005
    Inventors: Yoshikuni Watanabe, Nobuhiko Sato, Makoto Kitagawa, Tetsuya Hashimoto
  • Semiconductor substrate, semiconductor device, and method of manufacturing the same
    Publication number: 20040259315
    Abstract: A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 23, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Nobuhiko Sato
  • Shaver
    Publication number: 20040250430
    Abstract: The present invention relates to the shaver capable of cutting deeply, provided with the outer blade having a plurality of the hair-guiding ports and the inner blade being adjacently located to the inner part of the outer blade and relatively moving against the said inner part, serving like an electric shaver of rotation or motion, which consists in going back and forth adjacently, wherein there is provided an escaping gap for taking hairs out in one part between the outer and inner blades, thus hooking the hairs guided into the gap, on the tip of the inner blade or pinching them inside the escaping gap and afterward, taking out the hairs and beards from the root of hairs and when the hairs move to the region without any escaping gap, they will be cut in the deep location.
    Type: Application
    Filed: April 27, 2004
    Publication date: December 16, 2004
    Inventors: Teizoh Satoh, Nobuhiko Sato
  • Semiconductor member manufacturing method and semiconductor device manufacturing method
    Patent number: 6828214
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: December 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Semiconductor member manufacturing method and semiconductor device manufacturing method
    Publication number: 20040241398
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Member and member manufacturing method
    Publication number: 20040224489
    Abstract: A porous structure with high uniformity is provided even when evaluated at a high resolution (high evaluation standard) of several or several ten nm or less. By applying this porous structure to the manufacture of an SOI substrate, an SOI substrate which has an SOI layer with a small number of defects is provided. In a region at a depth of 5 to 10 nm from the surface of a porous Si layer, values of parameters such as porosity and the like which represent a porous structure are uniformed. The manufacture of an SOI substrate using this porous Si layer reduces recessed defects in an SOI layer.
    Type: Application
    Filed: May 5, 2004
    Publication date: November 11, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hajime Ikeda, Nobuhiko Sato, Kiyofumi Sakaguchi