Patents by Inventor Nobuhiko Sato

Nobuhiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6769179
    Abstract: The present invention relates to the shaver capable of cutting deeply, provided with the outer blade having a plurality of the hair-guiding ports and the inner blade being adjacently located to the inner part of the outer blade and relatively moving against the said inner part, serving like an electric shaver of rotation or motion, which consists in going back and forth adjacently, wherein there is provided an escaping gap for taking hairs out in one part between the outer and inner blades, thus hooking the hairs guided into the gap, on the tip of the inner blade or pinching them inside the escaping gap and afterward, taking out the hairs and beards from the root of hairs and when the hairs move to the region without any escaping gap, they will be cut in the deep location.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: August 3, 2004
    Inventors: Teizoh Satoh, Nobuhiko Sato
  • Patent number: 6750980
    Abstract: An information processing apparatus which outputs data to an electronic device. Information indicating a data processing ability of the electronic device is first obtained, whereupon data processing means is controlled so as to process the data output to the electronic device depending on the data processing ability indicated by the information so obtained.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: June 15, 2004
    Inventors: Akihiro Shimura, Satoshi Nagata, Yoshifumi Okamoto, Tetsuya Morita, Shunya Mitsuhashi, Nobuhiko Sato, Takanori Nishijima, Masaki Unishi
  • Patent number: 6717693
    Abstract: An information processing apparatus includes an acquiring unit for acquiring information from a printer connected through a bidirectional interface, and a control unit for controlling a display status of a virtual printer, which is displayed on a display screen and represents the printer, on the basis of the information acquired by the acquiring unit. An output apparatus includes a setting unit for setting an operating environment, and a changing unit for changing operating environment information set by the setting unit on the basis of information acquired from an information processing apparatus connected through a bidirectional interface.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: April 6, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunya Mitsuhashi, Satoshi Nagata, Yoshifumi Okamoto, Tetsuya Morita, Akihiro Shimura, Nobuhiko Sato, Takanori Nishijima, Masaki Unishi
  • Publication number: 20040061886
    Abstract: An information processing apparatus includes an acquiring unit for acquiring information stored in a memory of a printing device connected through a bidirectional interface, and a selecting unit for selecting a printer driver corresponding to the information acquired by the acquiring unit from a plurality of printer drivers on the basis of the information.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 1, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Satoshi Nagata, Yoshifumi Okamoto, Tetsuya Morita, Akihiro Shimura, Shunya Mitsuhashi, Takanori Nishijima, Masaki Unishi
  • Publication number: 20040048091
    Abstract: This invention includes a step of forming the first substrate which has a semiconductor region and an insulating region on its surface and a step of coating the first substrate with a single-crystal semiconductor layer. In the coating step, a single-crystal semiconductor is longitudinally grown in the semiconductor region and then laterally grown to manufacture a substrate.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 11, 2004
    Inventors: Nobuhiko Sato, Kiyofumi Sakaguchi
  • Patent number: 6667812
    Abstract: An information processing apparatus acquires identification information which specifies an interpreting program for interpreting a device control language, the specified interpreting program being operable in an external device connected to the information processing apparatus. It is discriminated whether a selected first control program corresponds to the device control language interpreted by the specified interpreting program. If it is discriminated that the selected first control program does not correspond to the device control language interpreted by the specified interpreting program, a second control program corresponding to the device control language interpreted by the specified interpreting program is selected from a plurality of control programs. Data is output to the external device using the first control program or, if it is discriminated that the first control program does not correspond to the device control language, the selected second control program.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: December 23, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Satoshi Nagata, Yoshifumi Okamoto, Tetsuya Morita, Akihiro Shimura, Shunya Mitsuhashi, Takanori Nishijima, Masaki Unishi
  • Patent number: 6660606
    Abstract: The number of defects (HF defects) in the SOI layer of an SOI substrate is reduced. In an annealing method of annealing an SOI substrate in a reducing atmosphere at a temperature equal to or less than the melting point of a semiconductor, annealing is executed in a state wherein a flow of a reducing atmospheric gas parallel to the surface of the SOI substrate is generated near this surface.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: December 9, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Miyabayashi, Nobuhiko Sato, Masataka Ito
  • Publication number: 20030205480
    Abstract: A porous layer having a multilayered structure is formed. An Si substrate (102) to be processed is anodized in a first electrolytic solution (141, 151) while being held between an anode (106) and a cathode (104) in an anodizing bath (101). The first electrolytic solution (141, 151) is exchanged with a second electrolytic solution (142, 152). The Si substrate (102) is anodized again, thereby forming a porous layer having a multilayered structure on the Si substrate (102).
    Type: Application
    Filed: June 11, 2003
    Publication date: November 6, 2003
    Inventors: Kiyofumi Sakaguchi, Nobuhiko Sato
  • Publication number: 20030201180
    Abstract: A capillary array capable of being easily mounted on an electrophoresis apparatus without damaging the capillaries. The capillary array can include a plurality of capillaries that can be fixed via hollow electrodes on a load header in a matrix arrangement. The load header can be disposed on the electrophoresis apparatus. The capillary array can include a capillary frame onto which a capillary head and a detection portion can be detachably mounted. The structure allows the load header, the capillary head, the detection unit and other portions of the capillary array to be handled as a unit, thereby making it easier to mount the capillary array on the electrophoresis apparatus.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 30, 2003
    Inventors: Takayasu Furukawa, Nobuhiko Sato, Syozo Kasai, Seiichi Ugai, Motohiro Yamazaki, Hiroyuki Tanaka, Yuki Nonaka, Yoshio Onodera, Noriyuki Shimoda
  • Patent number: 6639327
    Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: October 28, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutaka Momoi, Takao Yonehara, Nobuhiko Sato, Masataka Ito, Noriaki Honma
  • Patent number: 6633397
    Abstract: An output apparatus for forming output information on the basis of input information inputted from an external apparatus and outputting is constructed by a connector for connecting the output apparatus to the external apparatus so that they can communicate, a memory to store a data group to manage a menu structure for setting an output environment, an internal environment setting unit for setting an output environment on the basis of the data group, a transfer unit for transferring the data group from the memory to the external apparatus through the connector, and an external environment setting unit for setting an output environment onto the external apparatus on the basis of the data group transferred to the external apparatus. An operating method for the internal environment setting unit and an operating method for the external environment setting unit are identical.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: October 14, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuko Amano, Nobuhiko Sato
  • Publication number: 20030170990
    Abstract: A process for manufacturing a semiconductor substrate, comprising the step of preparing a first substrate which has a surface layer portion subjected to hydrogen annealing, the separation-layer formation step of implanting ions of hydrogen or the like into the first substrate from the side of the surface layer portion, thereby to form a separation layer, the adhesion step of bonding the first substrate and a second substrate to each other so that the surface layer portion may lie inside, thereby to form a multilayer structure, and the transfer step of separating the multilayer structure by utilizing the separation layer, thereby to transfer the less-defective layer of the surface layer portion onto the second substrate. The less-defective layer is a single-crystal silicon layer in which defects inherent in a bulk wafer, such as COPs and FPDs, are decreased.
    Type: Application
    Filed: May 17, 1999
    Publication date: September 11, 2003
    Inventors: KIYOFUMI SAKAGUCHI, TAKAO YONEHARA, NOBUHIKO SATO
  • Patent number: 6617378
    Abstract: A golf ball coating composition is obtained by incorporating in a base resin paint a fluorescent whitening agent which is a 7-triazinylamino-3-phenylcoumarin derivative. A golf ball painted on its cover surface with the coating composition is improved in weather resistance and brightness and minimized in color fading due to diffusion of the whitening agent into the cover.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: September 9, 2003
    Assignee: Bridgestone Sports Co., Ltd.
    Inventors: Takashi Ohira, Nobuhiko Sato
  • Patent number: 6616552
    Abstract: In a golf ball including a core and a cover of at least one layer, the cover layer is formed of a heated mixture of an ionomer resin and a metal salt such as magnesium stearate. The heated mixture exhibits such a crystal melting behavior that when measured by DSC, the difference between first and second peak temperature is up to 30° C. The ball is improved in resilience.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: September 9, 2003
    Assignee: Bridgestone Sports Co., Ltd.
    Inventors: Rinya Takesue, Yasushi Ichikawa, Shunichi Kashiwagi, Nobuhiko Sato
  • Patent number: 6613678
    Abstract: A process for manufacturing a semiconductor substrate, comprising the step of preparing a first substrate which has a surface layer portion subjected to hydrogen annealing, the separation-layer formation step of implanting ions of hydrogen or the like into the first substrate from the side of the surface layer portion, thereby to form a separation layer, the adhesion step of bonding the first substrate and a second substrate to each other so that the surface layer portion may lie inside, thereby to form a multilayer structure, and the transfer step of separating the multilayer structure by utilizing the separation layer, thereby to transfer the less-defective layer of the surface layer portion onto the second substrate. The less-defective layer is a single-crystal silicon layer in which defects inherent in a bulk wafer, such as COPs and FPDs, are decreased.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: September 2, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
  • Patent number: 6605518
    Abstract: To cause a crack at a fixed position in a separation layer, a method of separating a composite member includes the steps of forming a separation layer inside a composite member, forming inside the separation layer a stress riser layer in which an in-plane stress has concentratedly been produced to an extent that does not cause separation by the in-plane stress, and enlarging the in-plane stress to cause a crack in the stress riser layer, thereby separating the composite member.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: August 12, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuaki Ohmi, Katsumi Nakagawa, Nobuhiko Sato, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takao Yonehara
  • Patent number: 6606466
    Abstract: A printer and method for enabling a user to select a paper cassette containing paper available for an appropriate finishing process when the user is to select another paper cassette to continue printing, after the print process has been interrupted due to an empty paper cassette. The printer or method uses a table containing information about the types of paper mounted in respective paper cassettes and a table containing information about relationships between the paper types and the finishing processes executable on the respective types of paper. If no appropriate paper is detected in the current paper cassette, it is determined which paper cassette contains papers available for the specified paper finishing process, and then the appropriate paper cassette information is displayed.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 12, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Patent number: 6593211
    Abstract: There are disclosed a semiconductor substrate having a non-porous monocrystalline layer with reduced crystal defects on a porous silicon layer and a method of forming the substrate. The forming method comprises a heat treatment step of heat-treating a porous silicon layer in an atmosphere not containing a silicon-based gas and the step of growing a non-porous monocrystalline layer on the porous silicon layer, wherein the heat treatment is conducted under the conditions such that the etched thickness of the silicon layer is 2 nm or less and that the rate of change r of the surface pore density of the porous silicon layer (r=surface pore density after heat treatment/surface pore density before heat treatment) satisfies the relationship 1/10000≦r≦1.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: July 15, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Patent number: 6569748
    Abstract: There are provided a method of producing an SOI wafer of high quality with excellent controllability, productivity and economy and a wafer produced by such a method. In the method of producing a substrate utilizing wafer bonding, a first substrate member and a second substrate member are mutually bonded, and then the second substrate member is separated from the first substrate member at the interface of a first layer and a second layer formed on the main surface of the first substrate member, whereby the second layer is transferred onto the second substrate member. In the separation, the separation position at the interface of the first and the second layers is ensured by varying the porosity of a porous Si layer, forming an easily separable plane by the coagulation of pores in porous Si, effecting ion implantation to the interface or utilizing a heteroepitaxial interface.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: May 27, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Nobuhiko Sato
  • Publication number: 20030087503
    Abstract: A method for making a thin film semiconductor. The method includes the steps of making a semiconductor substrate having one or more layers of different porosity, and subsequently separating the layers along a line of relative weakness. This method is particularly well adapted to manufacturing Silicon-on-Insulator (SOI) structures.
    Type: Application
    Filed: March 1, 2002
    Publication date: May 8, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato