Patents by Inventor Noriaki Oda
Noriaki Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7432545Abstract: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.Type: GrantFiled: September 22, 2005Date of Patent: October 7, 2008Assignee: NEC Electronics CorporationInventors: Hiroaki Ohkubo, Noriaki Oda, Yasutaka Nakashiba
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Patent number: 7397125Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.Type: GrantFiled: January 22, 2004Date of Patent: July 8, 2008Assignee: NEC Electronics CorporationInventor: Noriaki Oda
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Publication number: 20080088023Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.Type: ApplicationFiled: December 7, 2007Publication date: April 17, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Noriaki ODA
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Publication number: 20080044997Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: ApplicationFiled: October 12, 2007Publication date: February 21, 2008Inventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
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Patent number: 7327031Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.Type: GrantFiled: September 30, 2004Date of Patent: February 5, 2008Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda
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Publication number: 20080017993Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.Type: ApplicationFiled: August 24, 2007Publication date: January 24, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Noriaki ODA
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Semiconductor device having an anti-oxidizing layer that inhibits corrosion of an interconnect layer
Patent number: 7312535Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: GrantFiled: March 18, 2004Date of Patent: December 25, 2007Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune -
Patent number: 7230337Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: GrantFiled: January 21, 2004Date of Patent: June 12, 2007Assignee: NEC Electronics CorporationInventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Publication number: 20070069388Abstract: In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Inventors: Hiroyuki Kunishima, Noriaki Oda
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Publication number: 20060276029Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: ApplicationFiled: August 15, 2006Publication date: December 7, 2006Inventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Publication number: 20060076596Abstract: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.Type: ApplicationFiled: September 22, 2005Publication date: April 13, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroaki Ohkubo, Noriaki Oda, Yasutaka Nakashiba
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Publication number: 20050218477Abstract: There is provided a semiconductor device excellent in reliability. The semiconductor device is comprised of a semiconductor substrate, an insulating portion having a multilayer insulating film composed of an etch stopper film, an insulating film, an etch stopper film, an insulating film, an etch stopper film and an insulating film provided on an upper portion of the semiconductor, fuses provided on the insulating portion, and a seal ring composed of a copper containing metal film, a barrier metal film, a copper containing metal film and a barrier metal film embedded in the insulating portion so as to surround a region just below the fuses.Type: ApplicationFiled: March 31, 2005Publication date: October 6, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki Takewaki, Noriaki Oda
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Publication number: 20050067700Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.Type: ApplicationFiled: September 30, 2004Publication date: March 31, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki Takewaki, Noriaki Oda
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Publication number: 20040251552Abstract: A semiconductor device includes a lower layer formed on a substrate and a first insulating layer formed to cover the lower layer. A first concave section is formed to extend from a surface of the first insulating layer to the lower layer. A first taper section is formed along a corner portion between a bottom of the first concave section and an inner wall of the first concave section, and has a taper surface which extends toward a center of the bottom. A first conductor section is formed of material containing copper to fill the first concave section in which the first taper section is formed.Type: ApplicationFiled: April 30, 2004Publication date: December 16, 2004Applicant: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Hiroyuki Kunishima, Noriaki Oda
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Publication number: 20040245643Abstract: A semiconductor device includes a first wiring layer section formed above a semiconductor substrate; and a second wiring layer section formed on the first wiring layer section. The latter includes a first interlayer insulating film; a plurality of first via-plugs formed in the first interlayer insulating film separated from each other by a first distance; and a plurality of first wiring lines formed on the plurality of first via-plugs in the first interlayer insulating film and connected with the plurality of first via-plugs. The second wiring layer section includes a second interlayer insulating film; a plurality of second via-plugs formed in the second interlayer insulating film, separated from each other by a second distance which is longer than the first distance; and a plurality of second wiring lines formed on the plurality of second via-plugs in the second interlayer insulating film and connected with the plurality of second via-plugs, respectively.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki Takewaki, Noriaki Oda, Ichiro Honma
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Patent number: 6821687Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.Type: GrantFiled: April 2, 2002Date of Patent: November 23, 2004Assignee: NEC Electronics CorporationInventors: Nobuaki Hamanaka, Takashi Yokoyama, Kazutoshi Shiba, Noriaki Oda
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Publication number: 20040188851Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: ApplicationFiled: March 18, 2004Publication date: September 30, 2004Applicant: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
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Publication number: 20040173910Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: ApplicationFiled: January 21, 2004Publication date: September 9, 2004Applicant: NEC Electronics CorporationInventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Patent number: 6777324Abstract: A semiconductor device having a multi-layer interconnection structure including bottom interconnects and top interconnects including a first top interconnect having a maximum thickness and a second top interconnect having a thickness thinner than that of the first top interconnect. Thereby, optimization of the parasitic capacitance and the parasitic resistance depending on the demand on the circuit operation and the interconnect length can be attained.Type: GrantFiled: December 9, 2002Date of Patent: August 17, 2004Assignee: NEC Electronics CorporationInventor: Noriaki Oda
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Publication number: 20040150112Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.Type: ApplicationFiled: January 22, 2004Publication date: August 5, 2004Applicant: NEC ELECTRONICS CORPORATIONInventor: Noriaki Oda