Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: A semiconductor device is provided and contains a substrate, a first wiring layer, a first oxide film, a dielectric film, a first nitrogen layer, a second wiring layer, a via hole, and a second nitrogen layer. The first wiring layer is formed on the substrate, and the first oxide film formed on the first wiring layer. The dielectric film has a low dielectric constant and is disposed between the first and second wiring layers. The first nitrogen layer contains nitrogen and is formed in the first oxide film. The via hole is formed through the dielectric film and is disposed between the first wiring layer and the second wiring layer for electrically connecting the first wiring layer and the second wiring layer. The second nitrogen layer contains nitrogen and is formed on a side wall of the via hole. Since the first and second nitrogen layers prevent moisture from spreading to various portions of the semiconductor device, leak current between adjacent wirings of the wiring layers is prevented.

Abstract: A semiconductor device having a multi-layer interconnection structure including bottom interconnects and top interconnects including a first top interconnect having a maximum thickness and a second top interconnect having a thickness thinner than that of the first top interconnect. Thereby, optimization of the parasitic capacitance and the parasitic resistance depending on the demand on the circuit operation and the interconnect length can be attained.

Abstract: Sides of via hole do not bow horizontally, thereby preventing an increase of a resistance of a wiring layer connected to a conductor in the via hole. A semiconductor device comprises a first wiring layer, an insulating layer over the first wiring, a second wiring on the insulating layer, a first hole formed in the first wiring, a second hole formed in the insulating layer connecting with at least a part of the first hole, and a conductive material in first and second holes that electrically connects the first wiring layer to the second wiring layer.

Abstract: Sides of via hole do not bow horizontally, thereby preventing an increase of a resistance of a wiring layer connected to a conductor in the via hole. A semiconductor device comprises a first wiring layer, an insulating layer over the first wiring, a second wiring on the insulating layer, a first hole formed in the first wiring, a second hole formed in the insulating layer connecting with at least a part of the first hole, and a conductive material in first and second holes that electrically connects the first wiring layer to the second wiring layer.

Abstract: A semiconductor device having a multi-layer interconnection structure including bottom interconnects and top interconnects including a first top interconnect having a maximum thickness and a second top interconnect having a thickness thinner than that of the first top interconnect. Thereby, optimization of the parasitic capacitance and the parasitic resistance depending on the demand on the circuit operation and the interconnect length can be attained.

Abstract: A logic cell library generating apparatus for calculating wiring resistance values using different values depending on the presence or absence of and/or the distance to an adjacent wire at respective positions of each wire to generate a logic cell library.

Abstract: In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

Abstract: A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.

Abstract: A silicon oxide film, a silicon oxynitride film, and a silicon oxide film are formed on a semiconductor substrate. A silicon nitride film and a silicon oxide film are formed, and, using an overlying resist film as a mask, are subjected to dry etching to form via-holes. Oxygen plasma ashing and resist removal are carried out. The silicon nitride film is subjected to dry etching to expose the surface of the copper film and the resist residue is removed. A tungsten film is then formed to bury the via-holes with tungsten. Excess tungsten film is removed by CMP and rinsing, thereby forming via-plugs that are composed of the tungsten film that remains in the via-holes. Silicon oxide film is formed over this structure. Using a resist film as a mask, wiring trenches are formed in the silicon oxide film. The resist film and etching residue are then removed. Amine removing solution that has entered seams in the tungsten film is vaporized by a heat treatment.

Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.

Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

Abstract: There is disclosed a semiconductor device which includes a semiconductor substrate having an element region and source and drain regions, a gate dielectric film containing nitrogen formed in the element region of said semiconductor substrate, a gate electrode formed on the gate dielectric film, a first dielectric film formed adjacent to the gate electrode so as to define a side wall therefor, a second dielectric film formed so as to cover the gate electrode and the first dielectric film, the second dielectric film being doped with nitrogen, and a third dielectric film formed so as to cover the second dielectric film, the third dielectric film being formed of silicon nitride. A method for manufacturing such a semiconductor device is also described.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.

Abstract: A semiconductor device comprises a wiring in each of one or more wiring layers formed on a semiconductor substrate, and wiring sidewall layers which are formed on side edge portions of the wiring and which include fluorine-containing silicon oxide. It is possible to form an inter-wiring insulating film comprising fluorine-containing silicon oxide or Hydroxy Silsesquioxane on the outer surface of the wiring sidewall layers. Further, it is possible to form thermally diffused regions of fluorine into which fluorine is thermally diffused from the wiring sidewall layers in the inter-wiring insulating layer and near the interfaces with the wiring sidewall layers.

Abstract: A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.

Abstract: The method of producing semiconductor device comprises ion implanting a first p-type impurity to form a p-type source-drain region 7 and a heat-treatment to activate followed by ion implantation of a second p-type impurity, ion-implanting a third impurity to convert the surface of at least a diffusion layer of a source-drain portion into amorphous to form titanium silicide 9. This reduces contact resistance between the titanium silicide layer and the p-type impurity layer to improve the current driving performance of the p-type MOS transistor.

Abstract: A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; forming a Ti-included layer in part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.

Abstract: A method of fabricating a semiconductor device is provided, which decreases the parasitic wiring capacitance among adjoining Cu-based wiring lines is provided and which prevents the oxidation of Cu-based wiring lines and the diffusion of the Cu atoms existing in the wiring lines.