Patents by Inventor Norio Kainuma
Norio Kainuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9547126Abstract: An optical waveguide sheet, includes: an optical path; and a clad member that covers the optical path, wherein the clad member has a portion formed by removing a part of the clad member which is on a first surface of an optical waveguide sheet on which the optical component is to be mounted and is provided within an area which is unused for propagation of light input to and output from the optical component.Type: GrantFiled: March 31, 2015Date of Patent: January 17, 2017Assignee: FUJITSU LIMITEDInventors: Sanae Iijima, Takashi Kubota, Norio Kainuma, Hidehiko Kira
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Patent number: 9536857Abstract: A heating header of a semiconductor mounting apparatus includes: a first material; and a second material, the second material being bonded to the first material and coming into contact with a first semiconductor chip when the first semiconductor chip is compressed, wherein a contact surface of the second material with the first semiconductor chip is a curved surface that is convex toward the first semiconductor chip side, and the contact surface of the second material with the first semiconductor chip becomes a planar surface when each temperature of the first material and the second material reaches a melting temperature of a solder that is formed between a first terminal of the first semiconductor chip and a second terminal of a second semiconductor chip.Type: GrantFiled: July 14, 2016Date of Patent: January 3, 2017Assignee: FUJITSU LIMITEDInventors: Hidehiko Kira, Takumi Masuyama, Norio Kainuma
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Publication number: 20160284566Abstract: A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.Type: ApplicationFiled: January 29, 2016Publication date: September 29, 2016Applicant: FUJITSU LIMITEDInventors: Hidehiko Kira, NORIO KAINUMA, TAKASHI KUBOTA, Takumi Masuyama
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Patent number: 9453973Abstract: A fabrication method for an optical connector, includes: inserting an optical waveguide sheet, in a direction of an optical path of the optical waveguide sheet, into an insertion hole of an optical connector including lenses disposed in a juxtaposed relationship on a first end face of the optical connector, the insertion hole extending from a second end face of the optical connector at an opposite side to the first end face toward the lenses; and performing first adjustment of adjusting a position of a tip end of the optical path with respect to the lenses by pressing a side end portion of the optical waveguide sheet inserted in the insertion hole from at least one of sides of a first direction along a disposition direction of the lenses, through a first hole portion that is provided in the optical connector and extends to the insertion hole.Type: GrantFiled: April 1, 2015Date of Patent: September 27, 2016Assignee: FUJITSU LIMITEDInventors: Takashi Kubota, Norio Kainuma, Sanae Iijima, Hidehiko Kira
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Publication number: 20160211243Abstract: A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a layer disposed between the first wiring layer and the second wiring layer, the layer includes an adhesive agent configured to bond the first wiring layer and the second wiring layer; a plurality of first bumps connected to the first wiring layer; a plurality of second bumps connected to the second wiring layer; and solder connected to the plurality of first bumps and the plurality of second bumps.Type: ApplicationFiled: December 15, 2015Publication date: July 21, 2016Applicant: FUJITSU LIMITEDInventors: MAKOTO SUWADA, Shunji Baba, TAKASHI KANDA, NORIO KAINUMA
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Publication number: 20150362675Abstract: An optical waveguide sheet, includes: an optical path; and a clad member that covers the optical path, wherein the clad member has a portion formed by removing a part of the clad member which is on a first surface of an optical waveguide sheet on which the optical component is to be mounted and is provided within an area which is unused for propagation of light input to and output from the optical component.Type: ApplicationFiled: March 31, 2015Publication date: December 17, 2015Applicant: Fujitsu LimitedInventors: Sanae IIJIMA, Takashi Kubota, Norio Kainuma, Hidehiko Kira
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Publication number: 20150346434Abstract: A fabrication method for an optical connector, includes: inserting an optical waveguide sheet, in a direction of an optical path of the optical waveguide sheet, into an insertion hole of an optical connector including lenses disposed in a juxtaposed relationship on a first end face of the optical connector, the insertion hole extending from a second end face of the optical connector at an opposite side to the first end face toward the lenses; and performing first adjustment of adjusting a position of a tip end of the optical path with respect to the lenses by pressing a side end portion of the optical waveguide sheet inserted in the insertion hole from at least one of sides of a first direction along a disposition direction of the lenses, through a first hole portion that is provided in the optical connector and extends to the insertion hole.Type: ApplicationFiled: April 1, 2015Publication date: December 3, 2015Applicant: FUJITSU LIMITEDInventors: Takashi Kubota, Norio Kainuma, Sanae Iijima, Hidehiko Kira
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Publication number: 20150212285Abstract: An optical module comprising: an optical waveguide transports light, the optical waveguide including a first mirror which reflects first light; an adhesive sheet formed over the optical waveguide, the adhesive sheet including a first gap above the first mirror; a first light-transmissive layer formed in the first gap; a lens sheet arranged over the adhesive sheet, the lens sheet including a first lens which is formed above the first light-transmissive layer; and a light-emitting device formed above the lens sheet, the light-emitting device including a light-emitting portion which emits the first light to the first lens.Type: ApplicationFiled: November 25, 2014Publication date: July 30, 2015Applicant: Fujitsu LimitedInventors: Norio Kainuma, Takashi Kubota
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Patent number: 9013048Abstract: A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer.Type: GrantFiled: February 28, 2014Date of Patent: April 21, 2015Assignee: Fujitsu LimitedInventor: Norio Kainuma
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Publication number: 20140339713Abstract: A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer.Type: ApplicationFiled: February 28, 2014Publication date: November 20, 2014Applicant: FUJITSU LIMITEDInventor: Norio KAINUMA
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Publication number: 20140103117Abstract: There is provided an RFID tag, which includes: a first substrate having flexibility and configured to include an antenna provided on a first surface of the first substrate; a second substrate; an IC chip mounted on a first surface of the second substrate; an anisotropic conductive rubber configured to contact the first substrate to the second substrate with the IC chip facing the first surface of the first substrate and to contact a terminal of the IC chip to the antenna; and an exterior rubber configured to cover the first substrate, the second substrate, and the IC chip.Type: ApplicationFiled: August 19, 2013Publication date: April 17, 2014Applicant: FUJITSU LIMITEDInventors: Shuichi TAKEUCHI, Norio KAINUMA, Kuniko ISHIKAWA, Tetsuya TAKAHASHI, Kenji KOBAE
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Patent number: 8076233Abstract: A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.Type: GrantFiled: September 17, 2009Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Kuniko Ishikawa, Norio Kainuma, Kenji Kobae
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Patent number: 7833831Abstract: An electronic component is equipped with electrode protrusions that make it possible to mount the electronic component without covering connection pads of a circuit board with solder and to dispose the connection pads of the circuit board with a narrow pitch while preventing electrical shorting of the connection electrodes during mounting. A method of manufacturing an electronic component equipped with connection electrodes, where electrode protrusions are covered with solder, includes a step of heating a solder sheet to a semi-molten state and pressing the electronic component onto the solder sheet to place the electrode protrusions in contact with the solder sheet and a step of retracting the electronic component from a position where the electrode protrusions contact the solder sheet to transfer solder onto outside surfaces of the electrode protrusions that contacted the solder sheet.Type: GrantFiled: December 6, 2007Date of Patent: November 16, 2010Assignee: Fujitsu LimitedInventors: Norio Kainuma, Kuniko Ishikawa, Hidehiko Kira
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Patent number: 7828193Abstract: In a method of mounting an electronic component on a substrate, electrode terminals on at least one of the substrate and the electronic component are composed of solder bumps. The electrode terminals of the substrate and the electrode terminals of the electronic component are placed in contact and ultrasonic vibration is applied to at least one of the substrate and the electronic component to provisionally bond the electrode terminals together. A gap between the substrate and the electronic component is then filled with flux fill, and the electrode terminals of the substrate and the electronic component are bonded by reflowing the solder bumps.Type: GrantFiled: December 14, 2007Date of Patent: November 9, 2010Assignee: Fujitsu LimitedInventors: Kuniko Ishikawa, Norio Kainuma, Hidehiko Kira
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Patent number: 7712650Abstract: When a semiconductor chip is mounted using ultrasonic vibration, a method of mounting makes it possible to bond the semiconductor chip and bonding patterns with sufficient bonding strength without making the construction of a circuit board complex. The method of mounting a semiconductor chip causes ultrasonic vibration to act on the semiconductor chip to mount the semiconductor chip on a circuit board by flip-chip bonding. As the circuit board, a circuit board is used where protrusion patterns are provided at positions on bonding patterns to which the semiconductor chip is bonded corresponding to antinodes of vibration for a case where the bonding patterns resonate due to ultrasonic vibration applied by the semiconductor chip.Type: GrantFiled: February 17, 2006Date of Patent: May 11, 2010Assignee: Fujitsu LimitedInventors: Takayoshi Matsumura, Kenji Kobae, Norio Kainuma, Kimio Nakamura
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Publication number: 20100075493Abstract: A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.Type: ApplicationFiled: September 17, 2009Publication date: March 25, 2010Applicant: FUJITSU LIMITEDInventors: Kuniko Ishikawa, Norio Kainuma, Kenji Kobae
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Patent number: 7566586Abstract: A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.Type: GrantFiled: December 6, 2006Date of Patent: July 28, 2009Assignee: Fujitsu LimitedInventors: Norio Kainuma, Hidehiko Kira, Kenji Kobae, Kimio Nakamura, Kuniko Ishikawa, Yukio Ozaki
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Publication number: 20090146652Abstract: A slider tester includes a driving unit that rotates a test medium, a set plate that detachably supports a slider as a single body, and an investigating apparatus that is electrically connected to the slider supported by the set plate and investigates the characteristics of the slider. A movable support part 30 that tiltably supports the slider is provided on the set plate. There is also provided a pressing mechanism that elastically presses the slider via the movable support part toward a surface of the medium to dispose the slider floating over the surface of the medium. The pressing mechanism includes an elastic body 56 composed of a plate spring that contacts the movable support part and elastically presses the movable support part.Type: ApplicationFiled: November 24, 2008Publication date: June 11, 2009Inventors: Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi, Shuichi Takeuchi, Takayoshi Matsumura, Hirokazu Yamanishi, Shinji Hiraoka, Yoshiaki Yanagida
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Publication number: 20090146653Abstract: A slider tester includes a driving unit that rotates a test medium, a set plate that detachably supports a slider as a single body, and an investigating apparatus that is electrically connected to the slider supported by the set plate and investigates the characteristics of the slider. A movable support part 30 that tiltably supports the slider is provided on the set plate. There is also provided a pressing mechanism that elastically presses the slider via the movable support part toward a surface of the medium to dispose the slider floating over the surface of the medium. The pressing mechanism includes an elastic body 56 composed of a plate spring that contacts the movable support part and elastically presses the movable support part.Type: ApplicationFiled: November 24, 2008Publication date: June 11, 2009Inventors: Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi, Shuichi Takeuchi, Takayoshi Matsumura, Hirokazu Yamanishi, Shinji Hiraoka, Yoshiaki Yanagida
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Patent number: 7514788Abstract: The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the electronic component are respectively flip-chip-bonded to electrodes of the circuit board by applying ultrasonic vibrations to the electronic component, and that a center of each of the bumps is previously relatively displaced, with respect to a center of each of the electrodes in a width direction, in a direction parallel to a direction of the ultrasonic vibrations.Type: GrantFiled: October 31, 2007Date of Patent: April 7, 2009Assignee: Fujitsu LimitedInventors: Kenji Kobae, Hidehiko Kira, Norio Kainuma, Takayoshi Matsumura