Patents by Inventor Norio Kainuma

Norio Kainuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040036994
    Abstract: The slider tester is capable of solely testing a slider and securely selecting good sliders so as to reduce wasteful costs. The slider tester, which tests reading and writing functions of a slider for reading data from and writing data on a recording medium, comprises: a testing device for testing the functions of the slider; and a setting plate holding the slider and electrically connecting the slider to the testing device, the setting plate separating the slider a prescribed distance from the recording medium during the test so as to read data from and write data on the recording medium, wherein the slider can be independently attached to and detached from the setting plate.
    Type: Application
    Filed: January 21, 2003
    Publication date: February 26, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Norio Kainuma, Hidehiko Kira, Shinji Hiraoka, Hirokazu Yamanishi, Atsushi Suzuki
  • Patent number: 6582993
    Abstract: Prior to setting of a semiconductor device upon the surface of a wiring substrate, the fluid of a light curable reaction resin is supplied from a nozzle to the surface of the wiring substrate. When the predetermined amount of the fluid has been discharged from the nozzle, the fluid within the nozzle is irradiated through a transparent window defined in the nozzle. A hardening reaction is induced in the irradiated segment of the fluid. The reduction in the fluidity can be achieved in the irradiated segment of the fluid. The irradiated segment forms a partition mass in the fluid within the nozzle. A reliable split can thus be achieved between the partition mass and the fluid discharged from the tip end of the nozzle. The split can be utilized to control the supplied amount of the fluid at a higher accuracy.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: June 24, 2003
    Assignee: Fujitsu Limited
    Inventors: Shunji Baba, Kenji Kobae, Hidehiko Kira, Norio Kainuma
  • Publication number: 20030057552
    Abstract: An apparatus and method for improving the underfill filling of a semiconductor chip element 100 which is ultrasonically bonded to and mounted on a circuit board. A semiconductor chip element 100 includes a silicon chip 101 and a group of stud bumps 117 formed on a bottom surface 101a of the chip 101. Signal stud bumps 113 are made of gold while power stud bumps 114, ground stud bumps 115 and dummy stud bumps 116 are all made of a gold-palladium alloy, which are harder than the signal stud bumps 113 and thus do not deform easily during ultrasonic treatment. Therefore, in a state in which the semiconductor chip element 100 is mounted, a gap of approximately 30 &mgr;m is maintained between the bottom surface 101a of the chip 100 and a top surface of the circuit board 120 on which the semiconductor chip element 100 is mounted.
    Type: Application
    Filed: August 20, 2002
    Publication date: March 27, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Norio Kainuma, Shunji Baba, Hidehiko Kira, Toru Okada
  • Publication number: 20020195476
    Abstract: A suspension of a head assembly provided in a disk apparatus is prevented from being deformed due to mounting of a head IC chip onto the suspension. The head IC chip mounted on the suspension has protruding electrodes made of gold. The suspension has electrode pads connected to the respective protruding electrodes of the head IC chip. Each of the electrode pads has a surface layer made of gold. The protruding electrodes of the head IC chip are bonded to the electrode pads of the suspension by ultrasonic bonding.
    Type: Application
    Filed: June 27, 2002
    Publication date: December 26, 2002
    Applicant: Fujitsu Limited
    Inventors: Shunji Baba, Hidehiko Kira, Norio Kainuma, Toru Okada
  • Patent number: 6483190
    Abstract: An apparatus and method for improving the underfill filling of a semiconductor chip element 100 which is ultrasonically bonded to and mounted on a circuit board. A semiconductor chip element 100 includes a silicon chip 101 and a group of stud bumps 117 formed on a bottom surface 101a of the chip 101. Signal stud bumps 113 are made of gold while power stud bumps 114, ground stud bumps 115 and dummy stud bumps 116 are all made of a gold-palladium alloy, which are harder than the signal stud bumps 113 and thus do not deform easily during ultrasonic treatment. Therefore, in a state in which the semiconductor chip element 100 is mounted, a gap of approximately 30 &mgr;m is maintained between the bottom surface 101a of the chip 100 and a top surface of the circuit board 120 on which the semiconductor chip element 100 is mounted.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Norio Kainuma, Shunji Baba, Hidehiko Kira, Toru Okada
  • Publication number: 20020164837
    Abstract: A method of mounting a semiconductor chip in which an IC chip is mounted by filling a gap between the chip and a substrate with adhesive which functions as an underfill. The fillet of the underfill is made to have a preferable shape. To accomplish this, a head IC chip provided with bumps is placed on a suspension that is covered with the underfill adhesive and is provided with pads. A bonding tool presses the head IC chip and applies ultrasonic oscillation to the head IC chip, so that the bumps are properly bonded to the pads. When the head IC chip is pressed and subjected to ultrasonic oscillation, the ultraviolet rays 108 are emitted so as to harden the peripheral portion 151a of the adhesive 151 spread out between the head IC chip 11 and the suspension 12.
    Type: Application
    Filed: July 3, 2002
    Publication date: November 7, 2002
    Applicant: Fujitsu Limited
    Inventors: Shunji Baba, Takatoyo Yamakami, Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi
  • Patent number: 6458237
    Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: October 1, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6437450
    Abstract: A method of mounting a semiconductor chip in which an IC chip is mounted by filling a gap between the chip and a substrate with adhesive which functions as an underfill. The fillet of the underfill is made to have a preferable shape. To accomplish this, a head IC chip provided with bumps is placed on a suspension that is covered with the underfill adhesive and is provided with pads. A bonding tool presses the head IC chip and applies ultrasonic oscillation to the head IC chip, so that the bumps are properly bonded to the pads. When the head IC chip is pressed and subjected to ultrasonic oscillation, the ultraviolet rays 108 are emitted so as to harden the peripheral portion 151a of the adhesive 151 spread out between the head IC chip 11 and the suspension 12.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: August 20, 2002
    Assignee: Fujitsu, Limited
    Inventors: Shunji Baba, Takatoyo Yamakami, Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi
  • Patent number: 6400529
    Abstract: A head assembly has a head slider including a magnetic head and a first electrode, an IC chip supporting the head slider on a principal surface of the IC chip, and a suspension supporting the IC chip, the IC chip comprising a second electrode and a third electrode on the principal surface thereof, the third electrode being connected to the suspension, the second electrode being electrically connected to the first electrode.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Shunji Baba, Hidehiko Kira, Norio Kainuma, Toru Okada
  • Patent number: 6369985
    Abstract: A head slider and head IC are mounted on a head suspension, the head IC being mounted on a head IC mounting surface. One or more through holes are provided on the head IC mounting surface of the head suspension and the head IC is mounted by injecting a bonding agent between the mounting surface and the head IC through the through holes. The bonding agent is evenly distributed beneath the head IC, so that the head suspension is well balanced.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 9, 2002
    Assignee: Fujitsu Limited
    Inventors: Akio Gouo, Hidehiko Kira, Norio Kainuma, Takeshi Ohwe
  • Publication number: 20020037363
    Abstract: A resin coating method for applying resin to a predetermined region of a wiring board includes the steps of imaging an external appearance of the resin extruded from a resin application device; and automatically adjusting an amount of the resin extruded from the resin application device based on the external appearance of the resin obtained in the imaging step.
    Type: Application
    Filed: March 20, 2001
    Publication date: March 28, 2002
    Inventors: Shunji Baba, Takatoyo Yamakami, Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi
  • Publication number: 20010040298
    Abstract: A wafer receiving conductive input/output bumps on the upward front side is placed on a platen. An underfill material sheet, adhered to the surface of the thin film tape, is superposed on the front side of the wafer. The underfill material sheet is forced to soften. When the underfill material sheet is urged against the wafer, the input/output bumps is allowed to penetrate through the underfill material sheet. After the underfill material is hardened, the thin film tape is peeled off from the hardened underfill material sheet. The underfill material can thus be supplied commonly to a large number of individual semiconductor chips included in the wafer. As compared with the case where the underfill material is supplied separately to the individual semiconductor chips, the working time can greatly be shortened.
    Type: Application
    Filed: January 4, 2001
    Publication date: November 15, 2001
    Inventors: Shunji Baba, Takatoyo Yamakami, Norio Kainuma, Kenji Kobae, Hidehiko Kira, Hiroshi Kobayashi
  • Publication number: 20010011774
    Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.
    Type: Application
    Filed: March 14, 2001
    Publication date: August 9, 2001
    Applicant: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6240634
    Abstract: In a method of production of a multichip package module, rough-pitch bare chips are positioned at first locations on a printed-circuit board, and the rough-pitch bare chips are temporarily attached to the board at the first locations. The rough-pitch bare chips are mounted on the board at the same time by applying heat and pressure to the rough-pitch bare chips simultaneously. A respective one of fine-pitch bare chips is positioned at a respective one of second locations on the board other than the first locations, and the respective one of the fine-pitch bare chips is mounted on the board by applying heat and pressure to the fine-pitch bare chips individually, in order to produce the multichip package module.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: June 5, 2001
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Kira, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6122823
    Abstract: In a method of production of a multichip package module, rough-pitch bare chips are positioned at first locations on a printed-circuit board, and the rough-pitch bare chips are temporarily attached to the board at the first locations. The rough-pitch bare chips are mounted on the board at the same time by applying heat and pressure to the rough-pitch bare chips simultaneously. A respective one of fine-pitch bare chips is positioned at a respective one of second locations on the board other than the first locations, and the respective one of the fine-pitch bare chips is mounted on the board by applying heat and pressure to the fine-pitch bare chips individually, in order to produce the multichip package module.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: September 26, 2000
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Kira, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6006426
    Abstract: In a method of production of a multichip package module, rough-pitch bare chips are positioned at first locations on a printed-circuit board, and the rough-pitch bare chips are temporarily attached to the board at the first locations. The rough-pitch bare chips are mounted on the board at the same time by applying heat and pressure to the rough-pitch bare chips simultaneously. A respective one of fine-pitch bare chips is positioned at a respective one of second locations on the board other than the first locations, and the respective one of the fine-pitch bare chips is mounted on the board by applying heat and pressure to the fine-pitch bare chips individually, in order to produce the multichip package module.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: December 28, 1999
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Kira, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 4629362
    Abstract: A shield tunneling machine in which a segment holding member is movable through a lifting beam in the radial direction of a shield frame so that the segment holding member holds a segment and sets it at a predetermined position in the circumferential direction of a tunnel within the shield frame; and an end balancer is pivotably connected to a base or root balancer which in turn is slidably mounted on the lifting beam so that the segment held by the segment holding member is correctly set at a predetermined position while the posture of the segment is suitably adjusted, whereby the erection and assembly of segments can be easily accomplished.
    Type: Grant
    Filed: July 25, 1985
    Date of Patent: December 16, 1986
    Assignees: Ishikawajima-Harima Jukogyo Kabushiki Kaisha, The Tokyo Electric Power Co., Inc.
    Inventors: Norio Kainuma, Takashi Sakuraya, Akira Tanaka, Yoshio Yanagi