BACK-SIDE DEVICE CONTACTS AROUND EPITAXIAL SOURCE/DRAIN
Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.
Latest Intel Patents:
- Fabrication of stackable embedded eDRAM using a binary alloy based on antimony
- Apparatus, system, and method of communicating an extremely high throughput (EHT) physical layer (PHY) protocol data unit (PPDU)
- Mode-1 downlink control information transmission-reception for configured sidelink scheduling in NR V2X
- Methods and apparatus to enhance an audio signal
- Network and edge acceleration tile (NEXT) architecture
Transistor cell density is an important characteristic in integrated circuits as increased cell density improves device capability. As cell density increases and transistor area decreases, scaling interconnects becomes increasingly difficult particularly with respect to achieving low resistance and necessary power delivery. Notably, back-side device contacts may be employed to provide such interconnects. For example, deep trench-like interconnects may be employed to provide power from the back-side of devices. However, such metal connections to distribute power from the back-side to the front-side of the transistor devices utilize significant cell area, which limits area scaling. Furthermore, current power connections may be shared by many devices, which creates resistance crowding effects. For example, when multiple nearby devices connected to a single power source draw power, undesirable voltage drops may occur. Also, capacitance penalties are significant with power rails at cell edges in close proximity to gate ends and/or active device areas.
It is desirable to provide source and drain contacts to transistor devices that offer increasing transistor cell density with optional contacts to each device source or drain for improved device performance. It is with respect to these and other considerations that the present improvements have been needed. Such improvements may become critical to increase cell density in higher performance integrated circuit electronic devices.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:
One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may also be employed in a variety of other systems and applications other than what is described herein.
Reference is made in the following detailed description to the accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout to indicate corresponding or analogous elements. It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, it is to be understood that other embodiments may be utilized, and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, over, under, and so on, may be used to facilitate the discussion of the drawings and embodiments and are not intended to restrict the application of claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter defined by the appended claims and their equivalents.
In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to “an embodiment” or “one embodiment” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms “over,” “under,” “between,” “on”, and/or the like, as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer.
Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features. The term immediately adjacent indicates such features are in direction contact. Furthermore, the terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value. The term layer as used herein may include a single material or multiple materials. As used in throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.
Transistor structures, device structures, apparatuses, integrated circuits, computing platforms, and methods are described herein related to metallization contacts to source or drain structures such that the metallization contacts a top surface of the source or drain structures, extends along a side surface of the source or drain structures, and contacts a back-side metal of the device. Such metallization contacts improve density, reduce contact resistance, and offer other advantages as discussed herein.
In some embodiments, a transistor structure includes a channel semiconductor between a source semiconductor and a drain semiconductor. The transistor structure has a front-side and a back-side with the front-side defined by a build up direction as well as being distal to a substrate on which the transistor structure is fabricated. The back-side is opposite the front-side. Notably, the transistor structure is typically contacted from the front-side during build up. The source and drain semiconductors may be epitaxial bodies including silicon and germanium (SiGe) such as epitaxial SiGe that is highly doped. One or both of the source semiconductor and drain semiconductor are contacted by a contact metallization that contacts a top surface of the source and/or drain semiconductor such that the top surface is proximal to the front-side of the transistor structure. The contact metallization further contacts a side surface of the source and/or drain semiconductor such that the contact metallization may be characterized as a direct metal wrap around connection to the source and/or drain semiconductor. The contact metallization extends beyond a bottom surface of the source and/or drain semiconductor to a back-side metal of the transistor structure. The term back-side metal indicates one or more metallization layers (e.g., metal lines interconnected by metal vias) over the back-side of the transistor structure. Such back-side metal may also be characterized as back-side interconnects or back-side interconnect layers. Similarly, a front-side metal indicates one or more metallization layers (e.g., metal lines interconnected by metal vias) over the front-side of the transistor structure and the front-side metal may be characterized as front-side interconnects, front-side interconnect layers, or the like. Thereby, a direct metal wrap around connection from back-side interconnect layers to a front-side of the source and/or drain semiconductor is provided. The front-side contact to the source and/or drain semiconductor may be characterized as a trench contact as the front-side contact is typically in a trench that extends perpendicular to the source-channel-drain direction of the transistor structure.
The techniques and transistor structures discussed herein may be employed to contact every or some device sources while enabling transistor cell scaling. Such increased scaling is enabled by creating a metal connection that wraps around the epitaxial source semiconductor, for example, to interconnect the front and back-side metal layers. Such connection minimizes cell area impacts. In some embodiments, the drain semiconductor is contacted only by the front-side metal layers while the source semiconductor is contacted only by the back-side metal layers using the discussed wrap around metallization contact. However, any combination of front-side and back-side connections to the source and drain semiconductors or the metallization contacts to the source and drain semiconductors may be employed.
In the illustrated example, transistor structure 100 includes a transistor 161 and a transistor 162 that have a shared drain contact 163 and a shared gate structure 141 with selective source contacts such that a source contact 116 is provided to transistor 161 and a source contact 115 is provided to transistor 162. Transistor 161 includes channel semiconductors 122 (e.g., nanoribbons) and transistor 162 includes channel semiconductors 124 (e.g., nanoribbons). Furthermore, transistor 161 includes a source 121 (e.g., a source semiconductor) and a drain 131 (e.g., a drain semiconductor) and transistor 162 includes a source 123 (e.g., a source semiconductor) and a drain 133 (e.g., a drain semiconductor). The source and drain semiconductors may be epitaxial bodies such as epitaxial silicon and germanium (SiGe), for example. In the illustrated example, channel semiconductors 122, 124 are at least partially embedded in sources 121, 123 and drains 131, 133. In some embodiments, channel semiconductors 122, 124 abut sources 121, 123 and drains 131, 133 and do not extend into sources 121, 123 and drains 131, 133.
As shown, source contact 115 has a portion 117 on (e.g., in contact with) a top surface 152 and a portion 114 that is on a side surface 153 of source 123 and extends to a back-side 151 metal interconnect 118. Portion 114 may be characterized as a deep via or deep contact and portion 117 may be characterized as a trench contact. Furthermore, source contact 116 is illustrated with only a trench contact but a deep contact portion 126 may be employed in some embodiments to contact source 121 to a back-side 151 metal interconnect 119. Absent deep contact portion 126, as shown, source 121 may be contacted by a metal contact 112 to a metal line 111 such that metal contact 112 and metal line 111 are a portion of front-side metal interconnect layer 102. Notably, a metal contact in analogy to metal contact 112 may be used to couple drain contact 163 to front-side metal interconnect layer 102. Furthermore, although illustrated with respect to source contacts, wrap around contact 115 may be employed for drain contacts in addition to or in the alternative to source contact applications.
As shown in
Turning to
Process 200 begins at operation 201, where a transistor structure work piece is received for processing. For example, transistor structures (e.g., NMOS and/or PMOS transistor structures) may be formed on and over a substrate. The substrate may include any suitable substrate such as a silicon wafer or the like. The transistor structures may be planar, multi-gate, or gate all around transistor structures formed using techniques known in the art. In the following, gate all around transistor structures are illustrated for the sake of clarity of presentation. In some embodiments, the transistor structure includes a one or more channel semiconductors covered by a gate structure or a dummy gate structure (which will later be removed and replaced by a gate structure). The transistor structure includes exposed portions of the one or more channel semiconductors and exposed portions of a substrate suitable for epitaxial growth of source and drain semiconductor bodies.
Processing continues at operation 202, where epitaxial source and drain semiconductor bodies are grown on the exposed channel semiconductor(s) and substrate portion. The epitaxial source and drain semiconductor bodies may be grown using any suitable technique or techniques. In some embodiments, epitaxial source and drain semiconductor bodies are grown from a single crystal substrate portion and/or single crystal channel semiconductor materials.
As shown, transistor structure 300 is formed on and over a substrate 301. Substrate 301 may include any suitable material and, in some embodiments, substrate 301 has the same or a similar composition with respect to channel regions 309. In some embodiments, substrate 301 and channel regions 309 include a Group IV material (e.g., silicon). In some embodiments, substrate 301 and channel regions 309 include a substantially monocrystalline material. In some embodiments, substrate 301 includes a buried insulator layer (e.g., SiO2), for example, of a semiconductor-on-insulator (SOI) substrate. Transistor structure 300 further includes a gate structure including a material 308 such as polysilicon and a hardmask 307 over material 308 and within sidewall spacers 306. Spacers 306 may include any suitable material such as silicon nitride (e.g., spacers 306 may include silicon and nitrogen). In some embodiments, spacer 306 extends over hardmask 307. In some embodiments, an additional layer may be provided over hardmask 307 that extends laterally over the top regions of spacers 306 adjacent hardmask 307. Notably, material 308 and hardmask 307 may be subsequently removed and replaced using replacement gate techniques or they may be formed over gate electrode and gate contact structures. In either event, the transistor structure 300, upon completion of fabrication may include a gate all around structure including a gate dielectric on channel regions 309 (and the channel regions of transistor 352) and a gate electrode on the gate dielectric. Furthermore, a gate contact (not shown) may contact the gate electrode.
Source 303, drain 305, source 304, and drain 302 may be formed on an exposed ridge 310 of substrate 301. For example, ridge 310 may be formed from substrate 301 using etch processing. Source 303, drain 305, source 304, and drain 302 may include any suitable source and drain materials. In some embodiments, an epitaxial silicon and germanium based material is used. In some embodiments, the source/drain semiconductor is a group IV materials (e.g., Si, Ge, SiGe), and/or group III-V materials (e.g., InGaAs, InAs). In some embodiments, the source and drain material employed is heavily-doped with electrically active impurities imparting n-type or p-type conductivity. For exemplary embodiments where transistor structure 100 is a conventional field effect transistor, both the source and drain semiconductor materials may be doped to the same conductivity type (e.g., n-type for NMOS and p-type for PMOS). In alternative embodiments (e.g., for a tunneling field effect transistor), the source/drain semiconductor materials may be doped complementarily. As shown, sources 303, 304 and drains 305, 302 may extend between adjacent portions of sidewall spacers 306.
In the context of transistor structure 300, source 303, drain 305, source 304, and drain 302 and portions of substrate 301 (or a dielectric on substrate 301, not shown) are exposed. Notably, subsequent processing may advantageously be self-aligned with trenches that expose source 303, drain 305, source 304, and drain 302.
Returning to
Returning to
Material plug 315 further remains on a side surface 333 of source 303 while being removed from an opposite side surface 321 of source 303. As illustrated herein, source 303, drain 305, source 304, and drain 302 may be faceted bodies due to their epitaxial growth. The terms top surface, side surface, bottom surface, and so on indicate surfaces that extend substantially in such directions and between points of the body defining an end of other adjacent surfaces. Furthermore, such surfaces need not be planar. For example, a top surface may be defined as a surface having a surface normal that is within 25° of the z-axis. Similarly, a side surface may be defined as a surface having a surface normal that is within 25° of the x-y plane. Therefore, the terms top surface, bottom surface, and side surface do not indicate that the surfaces are exactly parallel to any particular plane. For example, a top surface may be at or near a top of source 303 but a top surface does not necessarily run parallel to the x-y plane. Furthermore, a top surface need not include the top-most point of the body it references. Similarly, and as shown with respect to side surfaces 333, 321, a side surface may not extend parallel to the z-direction.
As discussed, material plug 315 is on at least a portion of top surface 320 and at least a portion of side surface 333. Material plug 315 also extends beyond a bottom of source 303 to a surface 334 that is substantially parallel with the x-y plane and that is at a height (in the z-dimension) at which ridge 310 begins to extend above a bulk of substrate 301. As is discussed further herein, the bulk of substrate 301 may be removed in back-side reveal processing to expose and isolate ridge 310. The corresponding conductive fill may also be exposed and extend beyond source 303 in the negative z-direction. As shown, capping layer 316 may extend over portions of spacer 306 and hardmask 307. Such processing may advantageously expand the patterning process window for improved process reliability.
Returning to
Notably, the formation of the dielectric material, if in contact with source 303, drain 305, source 304, and drain 302 may cause damage or other unwanted processing on the delicate epitaxial material thereof. For example, if exposed during dielectric material deposition, the epitaxial material of source 303, drain 305, source 304, and drain 302 may form unwanted oxide, which hinders electrical performance. Furthermore, if exposed during dielectric material deposition, the epitaxial material of source 303, drain 305, source 304, and drain 302 may be damaged, which may cause poor electrical performance or even device failure.
The conformal liner material may be formed using any suitable technique or techniques such as CVD or PVD. The conformal liner material may include any material layer or material stack that provides protection for source 303, drain 305, source 304, and drain 302. In some embodiments, the conformal liner material includes nitrogen. In some embodiments, the conformal liner material includes silicon and nitrogen. In some embodiments, the conformal liner material includes silicon nitride. In some embodiments, the conformal liner material includes aluminum and nitrogen. In some embodiments, the conformal liner material includes aluminum nitride. In some embodiments, the conformal liner material includes carbon. In some embodiments, the conformal liner material includes silicon and carbon. In some embodiments, the conformal liner material includes silicon carbide. Other materials may be employed.
As shown, protective conformal liner 318 is formed over and on exposed portions of material plug 315, capping layer 316, hardmask 307, spacer 306, source 303, drain 305, source 304, and drain 302. In the following, reference is made to source 303 and drain 305; however, such features may correspond to any sources and/or drains of transistor structure 317. For example, protective conformal liner 318 is on at least a portion of side surface 321 of source 303 and is optionally on a portion of top surface 320 of source 303. Furthermore, protective conformal liner 318 is on an exposed surface of ridge 310. Also as shown, protective conformal liner 318 is on a top surface and exposed side surfaces of drain 305 and drain 302.
Returning to
Returning to
Returning to
Returning to
Furthermore, contact metallization 329 extends below a bottom of source 303 for eventual back-side contact as discussed further herein below. As discussed, contact metallization 329 may include any suitable metal material or materials such as tungsten, cobalt, ruthenium, molybdenum, or the like. As shown, protective conformal liner 318 is on a side surface 319 of contact metallization 329 opposite side surface 333 with respect to contact metallization 329. Also as shown, sidewall surface side surface 321 of source 303 is absent contact metallization 329 while being covered by protective conformal liner 318 and dielectric fill material 323. As discussed, protective conformal liner 318 protects source 303 during application of dielectric fill material 323 to improve the electrical performance of source 303 in the implementation of contact metallization 329.
In some embodiments, a recess 330 (or gap) is provided above contact metallization 329 and between spacers 306 and dielectric fill material 323. In some embodiments, as shown, such recess processing may remove exposed portions of protective conformal liner 318. In other embodiments, protective conformal liner 318 remains on sidewall surfaces of dielectric fill material 323. In some embodiments, recess processing is not employed and a top surface of contact metallization 329 may be substantially planar with respect to spacers 306, hardmask 307, and dielectric fill material 323.
In some embodiments, such processing provides a deep via metallization adjacent side surface 333 of source 303. A trench contact metallization may also be provided on sources 303, 304 (as well as on drains 302, 305) as discussed with respect to
Returning to
Returning to
After formation of drain contact metallization 411, front-side metal interconnect layer 102 may be formed using any suitable technique or techniques such as dual-damascene processing or the like. As discussed, front-side metal interconnect layer 102 may include layers of metal lines and vias embedded in dielectric material and front-side metal interconnect layer 102 may provide routing to devices of an IC. The transistor structure work piece may then be attached to carrier substrate 101 using any suitable technique or techniques. Back-side processing such as back-side grind or back-side etch is then employed to remove portions of substrate 301 while leaving ridges 310, for example, as well as exposing a back-side region 403 of deep via contact metallization 329.
Discussion now turns to co-metallization processes for forming deep via contact metallization and trench metallization concurrently.
Furthermore, opening 512 of patterned layer 501 provides eventual contact metallization to drain 302, which may also be a trench contact extending across multiple drains such that the drains may share a contact. For example, with reference to
Trenches 504, 514 may be formed using any suitable technique or techniques such as selective and/or timed etch techniques. For example, a timed oxide etch may first be performed to form trenches 504, 514. For example, the oxide etch may be selective to etching oxide materials (e.g., that of dielectric fill material 323) to carbon based materials (e.g., that of material plug 315) and nitride materials (e.g., that of protective conformal liner 318). A nitride etch may then follow to remove protective conformal liner 318 and expose source 303 and drain 302. Material plug 315 is then removed as discussed with respect to operation 207 and
Integrated system 610 is further illustrated in the expanded view 620. In the exemplary embodiment, packaged device 650 (labeled “Memory/Processor” in
Functionally, PMIC 630 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 615 and with an output providing a current supply to other functional modules. In an embodiment, PMIC 630 may perform high voltage operations. As further illustrated, in the exemplary embodiment, RFIC 625 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 602.11 family), WiMAX (IEEE 602.16 family), IEEE 602.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of packaged device 650 or within a single IC (SoC) coupled to the package substrate of the packaged device 650.
In various examples, one or more communication chips 704, 705 may also be physically and/or electrically coupled to the motherboard 702. In further implementations, communication chips 704 may be part of processor 701. Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to motherboard 702. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 707, 708, non-volatile memory (e.g., ROM) 710, a graphics processor 712, flash memory, global positioning system (GPS) device 713, compass 714, a chipset 706, an antenna 716, a power amplifier 709, a touchscreen controller 711, a touchscreen display 717, a speaker 715, a camera 703, a battery 718, and a power supply 719, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.
Communication chips 704, 705 may enable wireless communications for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 704, 705 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 700 may include a plurality of communication chips 704, 705. For example, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. Furthermore, power supply 719 may convert a source power from a source voltage to one or more voltages employed by other devices of mobile computing platform 600. In some embodiments, power supply 719 converts an AC power to DC power. In some embodiments, power supply 719 converts an DC power to DC power at one or more different (lower) voltages. In some embodiments, multiple power supplies are staged to convert from AC to DC and then from DC at a higher voltage to DC at a lower voltage as specified by components of computing device 700.
While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.
In one or more first embodiments, a transistor structure having a front-side and a back-side comprises a channel semiconductor between a source semiconductor and a drain semiconductor, metallization in contact with a top surface and a first side surface of one of the source semiconductor or the drain semiconductor and in contact with a back-side metal interconnect over the back-side of the transistor structure such that the top surface is proximal to the front-side of the transistor structure, a conformal liner material on a second side surface, opposite the first side surface, of the source or drain semiconductor, and a dielectric material immediately adjacent the conformal liner material.
In one or more second embodiments, further to the first embodiment, the conformal liner material is on a third side surface of the metallization opposite the first side surface of the source semiconductor or the drain semiconductor.
In one or more third embodiments, further to the first or second embodiments, the source semiconductor or the drain semiconductor in contact with the metallization comprises silicon and germanium and the conformal liner material comprises silicon and nitrogen.
In one or more fourth embodiments, further to any of the first through third embodiments, the metallization extends over the conformal liner material on the second side surface and over a portion of the dielectric material immediately adjacent the conformal liner material.
In one or more fifth embodiments, further to any of the first through fourth embodiments, the metallization is a continuous metallization material absent a grain boundary therein.
In one or more sixth embodiments, further to any of the first through fifth embodiments, the metallization is in contact with a first region of the source semiconductor or the drain semiconductor, the first region comprising a recess in the source semiconductor or the drain semiconductor.
In one or more seventh embodiments, further to any of the first through sixth embodiments, the metallization is in contact with the source semiconductor, the transistor structure further comprises a second metallization in contact with the drain semiconductor, the metallization and second metallization both comprise a first composition, and the second metallization is in contact with a front-side metal layer of the transistor structure and absent a contact with a back-side metal layer comprising the back-side metal interconnect.
In one or more eighth embodiments, further to any of the first through seventh embodiments, the transistor structure further comprises a dielectric material between a top surface of the metallization and a front-side metallization layer of the transistor structure.
In one or more ninth embodiments, further to any of the first through eighth embodiments, the conformal liner material is on a portion of the drain semiconductor.
In one or more tenth embodiments, further to any of the first through ninth embodiments, the channel semiconductor comprises a first nanoribbon of a plurality of nanoribbons of the transistor structure.
In one or more eleventh embodiments, a system comprises a power supply and an integrated circuit die coupled to the power supply, the integrated circuit die comprising a transistor structure according to any of the first through eleventh embodiments.
In one or more twelfth embodiments, a method of fabricating an integrated circuit comprises receiving a transistor structure comprising a channel semiconductor between a source semiconductor and a drain semiconductor such that the source or drain semiconductor are exposed, patterning a material plug in contact with a top surface and a first side surface of one of the source semiconductor or the drain semiconductor, depositing a conformal liner material on exposed portions of the source semiconductor or the drain semiconductor and the material plug, the exposed portions including a second side surface of the source semiconductor or the drain semiconductor opposite the first surface, forming a dielectric material adjacent the conformal liner material on the second side surface, removing the material plug to form a deep via extending from over the top surface to below a bottom surface of the source semiconductor or the drain semiconductor, and filling the deep via with a contact metal.
In one or more thirteenth embodiments, further to the twelfth embodiment, the source semiconductor or the drain semiconductor in contact with the material plug comprises silicon and germanium and the conformal liner material comprises silicon and nitrogen.
In one or more fourteenth embodiments, further to the twelfth or thirteenth embodiments, the dielectric material comprises a flowable oxide material.
In one or more fifteenth embodiments, further to any of the twelfth through fourteenth embodiments, the method further comprises, prior to said removing the material plug, patterning the dielectric material adjacent the conformal liner material to form a trench over a portion of the top surface and extending over the dielectric material, such that said filling the deep via further comprises filling the trench with the contact metal.
In one or more sixteenth embodiments, further to any of the twelfth through fifteenth embodiments, the material plug is in contact with the source semiconductor, said patterning the dielectric material further forms a second trench to expose a second top portion of the drain semiconductor, and wherein said filling the deep via further comprises filling the second trench with the contact metal.
In one or more seventeenth embodiments, further to any of the twelfth through sixteenth embodiments, the method further comprises, prior to said filling the deep via, trimming an exposed portion of the source semiconductor or the drain semiconductor.
In one or more eighteenth embodiments, further to any of the twelfth through seventeenth embodiments, the method further comprises exposing a region of the contact metal proximal to the bottom surface of the source semiconductor or the drain semiconductor and contacting the region with a back-side metal.
It will be recognized that the invention is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above embodiments may include specific combination of features. However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
1. A transistor structure having a front-side and a back-side, the transistor structure comprising:
- a channel semiconductor between a source semiconductor and a drain semiconductor;
- metallization in contact with a top surface and a first side surface of one of the source semiconductor or the drain semiconductor and in contact with a back-side metal interconnect over the back-side of the transistor structure, wherein the top surface is proximal to the front-side of the transistor structure;
- a conformal liner material on a second side surface, opposite the first side surface, of the source or drain semiconductor; and
- a dielectric material immediately adjacent the conformal liner material.
2. The transistor structure of claim 1, wherein the conformal liner material is on a third side surface of the metallization opposite the first side surface of the source semiconductor or the drain semiconductor.
3. The transistor structure of claim 1, wherein the source semiconductor or the drain semiconductor in contact with the metallization comprises silicon and germanium and the conformal liner material comprises silicon and nitrogen.
4. The transistor structure of claim 1, wherein the metallization extends over the conformal liner material on the second side surface and over a portion of the dielectric material immediately adjacent the conformal liner material.
5. The transistor structure of claim 4, wherein the metallization is a continuous metallization material absent a grain boundary therein.
6. The transistor structure of claim 1, wherein the metallization is in contact with a first region of the source semiconductor or the drain semiconductor, the first region comprising a recess in the source semiconductor or the drain semiconductor.
7. The transistor structure of claim 1, wherein the metallization is in contact with the source semiconductor, the transistor structure further comprises a second metallization in contact with the drain semiconductor, the metallization and second metallization both comprise a first composition, and wherein the second metallization is in contact with a front-side metal layer of the transistor structure and absent a contact with a back-side metal layer comprising the back-side metal interconnect.
8. The transistor structure of claim 7, further comprising a dielectric material between a top surface of the metallization and a front-side metallization layer of the transistor structure.
9. The transistor structure of claim 7, wherein the conformal liner material is on a portion of the drain semiconductor.
10. The transistor structure of claim 1, wherein the channel semiconductor comprises a first nanoribbon of a plurality of nanoribbons of the transistor structure.
11. A system comprising:
- a power supply;
- an integrated circuit die coupled to the power supply, the integrated circuit die comprising a transistor structure having a front-side and a back-side, the transistor structure comprising: a channel semiconductor between a source semiconductor and a drain semiconductor; metallization in contact with a top surface and a first side surface of one of the source semiconductor or the drain semiconductor and in contact with a back-side metal over the back-side of the transistor structure, wherein the top surface is proximal to the front-side of the transistor structure; a conformal liner material on a second side surface, opposite the first side surface, of the source or drain semiconductor; and a dielectric material immediately adjacent the conformal liner material.
12. The system of claim 11, wherein the conformal liner material is on a third side surface of the metallization opposite the first side surface the first side surface of the source semiconductor or the drain semiconductor, and the source semiconductor or the drain semiconductor in contact with the metallization comprises silicon and germanium and the conformal liner material comprises silicon and nitrogen.
13. The system of claim 12, wherein the metallization extends over the conformal liner material on the second side surface and over a portion of the dielectric material immediately adjacent the conformal liner material, and the metallization is a continuous metallization material absent a grain boundary therein.
14. A method of fabricating an integrated circuit comprising:
- receiving a transistor structure comprising a channel semiconductor between a source semiconductor and a drain semiconductor, wherein the source or drain semiconductor are exposed;
- patterning a material plug in contact with a top surface and a first side surface of one of the source semiconductor or the drain semiconductor;
- depositing a conformal liner material on exposed portions of the source semiconductor or the drain semiconductor and the material plug, the exposed portions including a second side surface of the source semiconductor or the drain semiconductor opposite the first surface;
- forming a dielectric material adjacent the conformal liner material on the second side surface;
- removing the material plug to form a deep via extending from over the top surface to below a bottom surface of the source semiconductor or the drain semiconductor; and
- filling the deep via with a contact metal.
15. The method of claim 14, wherein the source semiconductor or the drain semiconductor in contact with the material plug comprises silicon and germanium and the conformal liner material comprises silicon and nitrogen.
16. The method of claim 14, wherein the dielectric material comprises a flowable oxide material.
17. The method of claim 14, further comprising, prior to said removing the material plug, patterning the dielectric material adjacent the conformal liner material to form a trench over a portion of the top surface and extending over the dielectric material, wherein said filling the deep via further comprises filling the trench with the contact metal.
18. The method of claim 17, wherein the material plug is in contact with the source semiconductor, said patterning the dielectric material further forms a second trench to expose a second top portion of the drain semiconductor, and wherein said filling the deep via further comprises filling the second trench with the contact metal.
19. The method of claim 14, further comprising, prior to said filling the deep via, trimming an exposed portion of the source semiconductor or the drain semiconductor.
20. The method of claim 14, further comprising:
- exposing a region of the contact metal proximal to the bottom surface of the source semiconductor or the drain semiconductor; and
- contacting the region with a back-side metal.
Type: Application
Filed: Jun 25, 2021
Publication Date: Dec 29, 2022
Applicant: Intel Corporation (Santa Clara, CA)
Inventors: Mohit Haran (Hillsboro, OR), Charles Wallace (Portland, OR), Leanord Guler (Hillsboro, OR), Sukru Yemenicioglu (Portland, OR), Mauro Kobrinsky (Portland, OR), Tahir Ghani (Portland, OR)
Application Number: 17/358,442