Abstract: A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.

Abstract: A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.

Abstract: A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.

Abstract: An edge damper frame 18b is disposed in between a part of an outer peripheral surface 20a of a frame-cover 20 and a leveling surface 14c-1 of a frame 14. A slope 18e of a diaphragm 15 is extended from the edge damper frame 18b toward the frame 14 and provided alongside an outer side surface 14c-2 of a convex portion 14c of the frame 14.

Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.

Abstract: An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

Abstract: Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.

Abstract: A starter which applies a mechanical rotating force to a rotor of an electromagnetic converter, such as a power generator, for startup of the rotor. The starter includes a startup spring (60) having an engaging portion (63) engageable with a 6th pinion (11a) of a wheel train coupled to the power generator. In interlock with the operation of pulling out a crown, a reset lever (70) is operated to bias the startup spring for engagement with the 6th pinion. Thereafter, the startup spring is released from the biased state in interlock with the operation of pushing in the crown. The startup spring is returned to the original position due to its own spring force, whereupon a mechanical rotating force is applied to the pinion. Since the rotating force can be set by a resilient force of only the startup spring, a stable rotating force is applied to the rotor (12).

Abstract: A method of fabrication of a semiconductor integrated circuit device, calls for disposing, in an ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, it is possible to prevent run-off of ionized amine into the ultrapure water.

Abstract: In a generator 120 in an electronic-controlled mechanical timepiece, the winding core 133b of a coil 134 arranged nearer to the perimeter of a base plate 2 is made shorter than the winding core 123b of a coil 124 arranged more inside. Accordingly, it is possible to make the area of an opening 2c can be made smaller in comparison with the prior art, and make the timepiece more small-sized by making smaller the outer diameter of the base plate 2 as keeping the distance D1 between the corner part of the opening 2c and the perimeter of the base plate 2 to the same degree as the prior art and thereby securing the strength of the base plate 2.

Abstract: Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.

Abstract: Systems and methods for pre-charging opposing nodes in a sense amplifier to substantially the same voltage in order to reduce or eliminate malfunctions arising from differences in threshold voltages of transistors coupled to the opposing nodes. One embodiment is a method including providing a silicon-on-insulator (SOI) sense amplifier having intermediate nodes between the transistors coupling each output data line to the corresponding input bit line and pre-charging each intermediate node to a predetermined voltage while the sense amplifier is not enabled. In one embodiment, the intermediate nodes are pre-charged by coupling them to a voltage source through pre-charge paths that do not include the data line pull-down transistors. In one embodiment, the method also includes decoupling the pre-charge paths after pre-charging the intermediate nodes and then enabling the sense amplifier.

Abstract: Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

Abstract: To provide an ink composition that when printed using a nozzle, does not cause clogging at the chip of the nozzle, is free from paper dependency, and when printed on an arbitrarily chosen paper, exhibits superior properties in water resistance, scratch resistance, lightfastness and ozone resistance and an inkjet recording method using it. The ink composition contains colored fine particles containing an oil-soluble polymer and an oil-soluble dye having an oxidation potential higher than 1.0 V (vs SCE), in an aqueous medium.

Abstract: A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.

Abstract: The speaker has a diaphragm main body 30 supported resiliently on a frame 23 via an edge portion 31 around its outer circumference, and the groove ribs 35 integrally formed in the edge portion 31, wherein a regulation member 37 for partially improving a flexural strength of the edge portion 31 is provided on a part of the front or back face of the edge portion 31.

Abstract: A valve device has a pressure chamber, which is connected to a liquid inlet and a liquid outlet and retains liquid, and a pressure regulator decreasing the pressure in the pressure chamber to a predetermined level. The pressure regulator has a pressure receiving member. When the pressure in the pressure chamber becomes lower than the predetermined level, the pressure receiving member is elastically deformed in an inward direction of the pressure chamber. The pressure regulator generates actuation force greater than the pressing force produced by the elastic deformation of the pressure receiving member. The pressure regulator is configured to be opened by the actuation force. When the pressure regulator is open, a fluid supply from the liquid inlet to the pressure chamber is permitted. It is thus possible to minimize the valve device.

Abstract: A speaker apparatus includes an elliptical-shaped or a round-edged rectangular-shaped vibration plate; an edge damper portion disposed on an outer peripheral edge portion of the vibration plate; a recessed portion formed between said vibration plate and said edge damper portion, having a caliber of a shape corresponding to the shape of said vibration plate; and an air core voice coil fitted into an interior of said recessed portion. The speaker apparatus further includes a frame for mounting said edge damper portion to support said vibration plate, having a stepped portion and a vertical wall portion; and an edge damper frame arranged on an outer periphery of said edge damper portion, having a support portion placed on the stepped portion and a rising portion being in contact with the vertical wall portion.

Abstract: A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals.

Abstract: A CPU 41 of a server device 40 measures an elapsed time after transmitting a data segment, and suspends measuring time upon receiving an acknowledgement segment for the data segment. CPU 41 transmits a data segment whose elapsed time has reached a retransmission timeout value. CPU 41 sets, as a retransmission timeout value of a data block, a time value determined according to a monotonically increasing function of a number of transmissions of the data block, during a given time period after the second-time transmission of the data block, while CPU 41 sets a time value which is predetermined and is different from the time value determined by the monotonically increasing function during a period between the first-time transmission and immediately before the second-time transmission of the data block.