Abstract: A brushless motor that is highly waterproof and highly watertight is provided. The brushless motor has a casing 1 configured to incorporate and hold a circuit board 4 and to support a rotor 3 rotatably. The casing 1 is configured such that the first annular wall 21a of a motor cover 21 is secured in part to the inner circumferential surface of the second annular wall 22a of a board cover 22. The first annular wall 21a has an annular groove 21c in its outer circumferential surface. An O-ring 23 is fitted in the annular groove 21c, accomplishing a highly waterproof and watertight sealing between the motor cover 21 and the board cover 22.

Abstract: A brushless motor according to the present invention has a relatively simple structure and its electrical connection parts can be surely connected by an easy work. A board-side connector 28 attached to a circuit board 4 is screw-fixed to a motor cover 21 together with the circuit board 4. A cover-side connector 29 to be fitted to the board-side connector 28 and an external connector connection part 30 connected to the cover-side connector 29 are provided on a board cover 22 by integral molding. When the motor cover 21 and the board cover 22 are fitted and assembled, the board-side connector 28 and the cover-side connector 29 are fitted to each other at the same time, and then a not-shown external connector is connected to the external connector connection part 30, whereby the supply of power and signals from an external part is enabled.

Abstract: The present invention realizes improved workability of electrical connection between an exciting coil and a circuit board disposed in a casing and ensures waterproofing of a connection portion. A waterproof case 25 in which a terminal bar 24 is buried is composed of a large-diameter portion 25a in a hollow bottomed-cylindrical shape and a small-diameter portion 25b around whose outer peripheral surface an O-ring 27 is fitted. A U-shaped end of the terminal bar 24 connected to an end of an exciting coil 7 is positioned in the hollow portion of the large-diameter portion 25a, part of a substantially linear portion extending from the U-shaped end of the terminal bar 24 is buried in the small-diameter portion 25b in an axial direction, and the other portion of the terminal bar 24 protrudes from the small-diameter portion 25b.

Abstract: A step of forming an insulating resin layer 31 includes a process of forming the insulating resin layer 31 made of a photo-sensitive resin on a load beam or a flexure 11 and an exposing and developing process in which a photo-mask 32 having different light transmittance between a part corresponding to a part near a slider mounting part 22 and other parts is applied to the insulating resin layer 31, exposed and developed so that the thickness of the insulating resin layer 31 of the part near the slider mounting part 22 is smaller than the thickness of the insulating resin layer 31 of other parts.

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract: A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.

Abstract: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

Abstract: The present invention provides a nickel-zinc battery of an inside-out structure, that is, a battery comprising a positive electrode containing beta-type nickel oxyhydroxide and a negative electrode containing zinc and having a similar structure to an alkali manganese battery, in which the beta-type nickel oxyhydroxide consists of substantially spherical particles, mean particle size of which is within a range from 19 ?m to a maximum of 40 ?m, the bulk density of which is within a range from 1.6 g/cm3 to a maximum of 2.2 g/cm3, tap density of which is within a range from 2.2 g/cm3 to a maximum of 2.7 g/cm3, specific surface area which based on BET method is within a range from 3 m2/g to a maximum of 50 m2/g, and the positive electrode of the nickel zinc battery contains graphite powder, where the weight ratio of graphite powder against a total weight of the positive electrode is defined within a range from 4% to a maximum of 8%.

Abstract: An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

Abstract: A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

Abstract: Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

Abstract: A battery pack is provided. For example, the battery pack includes a box-shaped or plate-shaped battery pack. The battery pack has a hard outer jacket member, a box-shaped or plate-shaped battery element, a cover, and a circuit board. The hard outer jacket member has a first opening and a second opening formed at both ends. The box-shaped or plate-shaped battery element is contained in the outer jacket member and has electrode terminals. The cover is molded from resin and is fitted to the first opening. The circuit board is connected to the electrode terminal leads and contained in the cover. At least the electrode terminal leads extends from the first opening. The cover has concave portions on both ends of one longer side. The outer jacket member has cut portions that expose at least the concave portions of the cover. At least a longer side of the cover and the outer jacket member are heat-adhered.

Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

Abstract: Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

Abstract: Systems and methods for forwarding instruction results from various pipeline stages to the initial stages of the pipelines, where the results can be used in the execution of subsequent instructions. In one embodiment, a forwarding mechanism is designed so that sets of one or more dynamic data selection circuits are placed in an alternating linear series with corresponding data registers. Each data register may be coupled to several dynamic data selection circuits, each of which corresponds to a different port or destination register. The dynamic data selection circuits coupled to a single data register are successively positioned in a direction that is perpendicular to the direction of the alternating linear array. Each dynamic data selection circuit may consist of a 2-input NOR gate coupled to drive a discharge transistor. The dynamic data selection circuits themselves may be aligned with the alternating series of latches and data selection circuits.

Abstract: Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

Abstract: Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

Abstract: A voice output system and method provide a voice of high quality while enabling coexistence with other wireless transmission systems. Compression-encoded voice data accompanying a video displayed on a video display surface is acquired at the side opposed to the video display surface. The voice data is wirelessly transmitted. At least at the video display surface side, the wirelessly transmitted voice data transmitted is received and expanded. Then, the voice based on the acquired expanded voice data is output.

Abstract: Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.

Abstract: A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can be boost the signals and provide the proper true or complement data to the data latches. To reduce the number of inverters, the register files are configured to output true and complement signals. Therefore, power consumption and area are reduced with the elimination of the inverters.