Abstract: Disclosed herein are power amplification systems that are dynamically biased based on a signal indicative of an envelope of the signal being amplified. The power amplification systems include a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal. The power amplification systems also include a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal. The biasing signal can improve or enhance the linearity of the power amplification systems.

Abstract: A linearization circuit reduces intermodulation distortion in a differential amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the differential amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the differential amplifier.

Abstract: Disclosed herein are power amplification (PA) systems configured to amplify a signal, such as a radio-frequency signal. The PA system includes a plurality of power amplifiers that are configured to amplify a signal received at a signal input and to output the amplified signal at a signal output. The power amplifiers are configured to receive a supply voltage that is a combination of a battery voltage and an envelope tracking signal. The PA system includes a PA controller configured to control the power amplifiers based at least in part on the battery voltage or a power output of the power amplifiers. The PA controller can be configured to alter impedance matching components of the PA system to reconfigure a load line of the power amplifiers.

Abstract: Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Abstract: Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Abstract: Transformer-based Doherty power amplifier (PA). In some embodiments, a Doherty PA can include a carrier amplification path having an output that includes a carrier transformer, and a peaking amplification path having an output that includes a peaking transformer. The Doherty PA can further include a combiner configured to combine the outputs of the carrier and peaking amplification paths into an output node. The combiner can include a quarter-wave circuit implemented between the carrier and peaking transformers.

Abstract: Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.

Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Abstract: Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

Abstract: Envelope tracking can be employed to reduce power consumption of a power amplifier, but envelope tracking can introduce nonlinearities to a power amplifier. These nonlinearities can manifest themselves as noise at the output of the power amplifier. Embodiments described herein provide techniques for characterizing a parameter indicative of power amplifier noise when envelope tracking is employed. Measurement of this parameter can permit power amplifier designers to decide whether to forgo envelope tracking if a power amplifier is too susceptible to such noise, redesign the power amplifier to improve compatibility with envelope tracking, or to employ distortion compensation circuitry to reduce the noise output by the power amplifier. Counterintuitively, this distortion compensation circuitry may involve increasing the power, such as the envelope tracking power supply. However, increasing the power may be a desirable trade-off for increased linearity.

Abstract: Apparatus and methods for biasing of power amplifiers are disclosed. In one embodiment, a mobile device includes a transceiver that generates a radio frequency signal and a power amplifier enable signal, a power amplifier that provides amplification to the radio frequency signal and that is biased by a bias signal, and a bias circuit that receives the power amplifier enable signal and generates the bias signal. The bias circuit includes a gain correction circuit that generates a correction current in response to activation of the power amplifier enable signal, and a primary biasing circuit that generates the bias signal based on the correction current and the power amplifier enable signal.

Abstract: Disclosed herein are power amplification (PA) systems configured to amplify a signal, such as a radio-frequency signal. The PA system includes a plurality of power amplifiers that are configured to amplify a signal received at a signal input and to output the amplified signal at a signal output. The power amplifiers are configured to receive a supply voltage that is a combination of a battery voltage and an envelope tracking signal. The PA system includes a PA controller configured to control the power amplifiers based at least in part on the battery voltage or a power output of the power amplifiers. The PA controller can be configured to alter impedance matching components of the PA system to reconfigure a load line of the power amplifiers.

Abstract: A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

Abstract: A linearization circuit reduces intermodulation distortion in a parallel amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the parallel amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the parallel amplifier.

Abstract: A linearization circuit reduces intermodulation distortion in a differential amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the differential amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the differential amplifier.

Abstract: A linearization circuit reduces intermodulation distortion in a cascade amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the cascade amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the cascade amplifier.

Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.

Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.

Abstract: Transformer-based Doherty power amplifier (PA). In some embodiments, a Doherty PA can include a carrier amplification path having an output that includes a carrier transformer, and a peaking amplification path having an output that includes a peaking transformer. The Doherty PA can further include a combiner configured to combine the outputs of the carrier and peaking amplification paths into an output node. The combiner can include a quarter-wave circuit implemented between the carrier and peaking transformers.

Abstract: Microelectromechanical systems (MEMS) having contaminant control features. In some embodiments, a MEMS die can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS die can further include a contaminant control component implemented relative to the electromechanical assembly. The contaminant control component can be configured to move contaminants relative to the electromechanical assembly. For example, such contaminants can be moved away from the electromechanical assembly.