Patents by Inventor Pei Yu

Pei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234595
    Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.
    Type: Application
    Filed: May 22, 2024
    Publication date: July 17, 2025
    Inventors: Hsien-Chih HUANG, Guang-Lin CHEN, Pei-Yu WANG, Chia-Hao YU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250226271
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: March 25, 2025
    Publication date: July 10, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Publication number: 20250225101
    Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 10, 2025
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
  • Publication number: 20250225100
    Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 10, 2025
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
  • Publication number: 20250215279
    Abstract: A pressure-sensitive adhesive tape, a method for producing the same, and a method for using the same are provided. The pressure-sensitive adhesive tape includes a support layer, an adhesive layer, and a peeling layer. Solid components of the adhesive layer include a self-crosslinking acrylic resin, acrylate monomers or oligomers of the acrylate monomers, an isocyanate cross-linking agent, and a photo-initiator. Before the adhesive layer is irradiated by ultraviolet light, the acrylate monomers or the oligomers do not undergo a cross-linking and curing reaction. After the adhesive layer is irradiated by the ultraviolet light, the photo-initiator generates free radicals with abilities to initiate polymerization, and the self-crosslinking acrylic resin, the acrylate monomers or the oligomers, and the isocyanate cross-linking agent undergo the cross-linking and curing reaction, so that an adhesion of the adhesive layer is reduced.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 3, 2025
    Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, PEI-YU CHIANG
  • Patent number: 12347690
    Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.
    Type: Grant
    Filed: May 23, 2024
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20250203955
    Abstract: A device and method of forming a device are provided. The method includes forming a stack of nanostructure channels over a substrate by forming a source/drain opening. The method also includes forming a sacrificial source/drain in the source/drain opening. The method further includes increasing tensile strain of the stack of nanostructure channels by replacing the sacrificial source/drain with a replacement source/drain having germanium concentration that exceeds that of the sacrificial source/drain.
    Type: Application
    Filed: June 4, 2024
    Publication date: June 19, 2025
    Inventors: Hsien-Chih HUANG, Guan-Lin CHEN, Chia-Hao YU, Pei-Yu WANG, Chih-Hao WANG
  • Publication number: 20250203970
    Abstract: A method for fabricating a semiconductor device is disclosed. The method involves forming a stack of alternating semiconductor channels and interposers on a substrate, with sacrificial structures between the interposers. Source/drain openings are formed, and strain in the channels is modified. Source/drain structures are formed in the openings, and dielectric layers are deposited. The resulting device features stacked nanostructures with inner spacers of varying heights, enabling improved performance in electronic devices.
    Type: Application
    Filed: May 30, 2024
    Publication date: June 19, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Chia-Hao YU, Pei-Yu WANG, Hsien-Chih HUANG
  • Publication number: 20250183159
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.
    Type: Application
    Filed: January 30, 2025
    Publication date: June 5, 2025
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Patent number: 12318255
    Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: June 3, 2025
    Assignee: AmCad BioMed Corporation
    Inventors: Argon Chen, Yi-li Lee, Pei-Yu Chao, Wei-Hao Chen, Wei-Yu Hsu
  • Patent number: 12299007
    Abstract: A computer-implemented method, system and computer program product for automatically drawing infographics. Variables of a dataset are received from a computing device that were selected by the user of the computing device. For those selected variables that are associated with a data model, a procedure to draw infographics for variables assigned or not assigned the role of a target using the data model associated with each of the variables assigned or not assigned the role of target, respectively, is implemented. Alternatively, if the selected variables are not associated with a data model, then such variables are assigned a level of measurement as well as assigned the role of input. Such assignments become the data model which, along with the metadata (e.g., values of the variable) obtained by parsing the original data, are used to implement the procedure to draw infographics for variables not assigned the role of a target.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 13, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ye Fan, Qi Mao, Juan Wu, Jia Zhong Wu, Long Fan, Chong Liu, Wen Pei Yu, Yang Yang
  • Publication number: 20250151326
    Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.
    Type: Application
    Filed: April 25, 2024
    Publication date: May 8, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Pei-Yu WANG, Hsien-Chih HUANG, Chia-Hao YU
  • Patent number: 12293916
    Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Yu Chou, Tze-Liang Lee
  • Patent number: 12293438
    Abstract: In an approach for post-modeling data visualization and analysis, a processor presents a first visualization of a training dataset in a first plot. Responsive to receiving a selection of a data group of the training dataset to analyze, a processor identifies three or fewer key model features of the data group of the training dataset. A processor ascertains a representative record of each key model feature of the three or fewer key model features using a Local Interpretable Model-Agnostic Explanation technique. A processor presents a second visualization of the three or fewer key model features and the representative record of each key model feature in a second plot.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: May 6, 2025
    Assignee: International Business Machines Corporation
    Inventors: Wen Pei Yu, Xiao Ming Ma, Xue Ying Zhang, Si Er Han, Jing James Xu, Jing Xu, Jun Wang
  • Patent number: 12292850
    Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: May 6, 2025
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
  • Publication number: 20250137925
    Abstract: The present disclosure provides a detection and analysis method for rapid delineation of aging stages of styrene-butadiene-styrene (SBS) modified asphalt, including the following steps: performing a Fourier transform infrared spectroscopy (FTIR) test on unaged SBS-modified asphalt samples to obtain a copolymer index of IB0/S0 and neat asphalt functional group indexes, including the SI0, IB, aI0, ARI0, and CI0; performing the FTIR test on the aged SBS-modified asphalt samples to obtain an actual index of IB/S, SI, IB, aI, ARI, and CI; and delineating three aging stages of SBS-modified asphalt, including a polymer swelling stage, a polymer degradation stage and a component imbalance stage according to changes of functional group indexes. According to the present disclosure, the actual aging stages of the SBS-modified asphalt can be determined rapidly and accurately, providing a reasonable basis for the decision on pavement maintenance timing and mode.
    Type: Application
    Filed: October 28, 2024
    Publication date: May 1, 2025
    Inventors: Derun Zhang, Peixin Xu, Ziyang Liu, Dongxing Luan, Zheng Liu, Yichen Guo, Pei Yu, Jinbiao Tang, Qisheng Hu, Chenhui Peng
  • Patent number: 12280372
    Abstract: The present invention relates to a near-field acoustic platform capable of synthesizing high resolution, arbitrarily shaped energy potential wells. A thin and viscoelastic membrane is utilized to modulate acoustic wavefront on a deep, sub-wavelength scale by suppressing the structural vibration selectively on the platform. This new acoustic wavefront modulation mechanism is powerful for manufacturing complex biologic products.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 22, 2025
    Assignee: The Regents of the University of California
    Inventors: Pei Yu E. Chiou, Kuan-Wen Tung, Benjamin M. Wu
  • Patent number: 12276605
    Abstract: The present disclosure provides a detection and analysis method for rapid delineation of aging stages of styrene-butadiene-styrene (SBS) modified asphalt, including the following steps: performing a Fourier transform infrared spectroscopy (FTIR) test on unaged SBS-modified asphalt samples to obtain a copolymer index of IB0/S0 and neat asphalt functional group indexes, including the SI0, IB, aI0, ARI0, and CI0; performing the FTIR test on the aged SBS-modified asphalt samples to obtain an actual index of IB/S, SI, IB, aI, ARI, and CI; and delineating three aging stages of SBS-modified asphalt, including a polymer swelling stage, a polymer degradation stage and a component imbalance stage according to changes of functional group indexes. According to the present disclosure, the actual aging stages of the SBS-modified asphalt can be determined rapidly and accurately, providing a reasonable basis for the decision on pavement maintenance timing and mode.
    Type: Grant
    Filed: October 28, 2024
    Date of Patent: April 15, 2025
    Assignee: Huazhong University of Science and Technology
    Inventors: Derun Zhang, Peixin Xu, Ziyang Liu, Dongxing Luan, Zheng Liu, Yichen Guo, Pei Yu, Jinbiao Tang, Qisheng Hu, Chenhui Peng
  • Patent number: 12261089
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: March 25, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Publication number: 20250095690
    Abstract: Provided are systems and methods for the automatic generation of support videos from a source video. For example, the support video can more deeply explain or elaborate upon content included in source video. In particular, a computing system can obtain a source video and extract one or more sets of textual content associated with the source video. For example, the sets of textual content can include a transcript of speech that occurs within the source video. The computing system can process the one or more sets of textual content with a generative sequence processing model to generate, as an output of the generative sequence processing model, additional textual content for a support video.
    Type: Application
    Filed: September 16, 2024
    Publication date: March 20, 2025
    Inventors: Pei-Yu Chi, Sen-Po Hu, Irfan Aziz Essa, Tao Dong