Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A method according to the present disclosure includes providing a workpiece. The workpiece includes a fin-shaped structure including a channel region and a source/drain region, a metal gate structure disposed over the channel region, a dummy source/drain feature disposed over the source/drain region, and a dielectric structure disposed over the dummy source/drain feature. The method further includes forming a trench through the dielectric structure and the dummy source/drain feature to expose a sidewall of the channel region, forming an epitaxial layer over the sidewall of the channel region, and forming a metal feature over a sidewall of the epitaxial layer and in the trench.

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.

Abstract: Disclosed are a method for whole blood filtration and a filter membrane structure for whole blood filtration, specifically including the following steps: (1) a filter membrane structure made up of at least two filtration membranes sequentially stacked from top to bottom is selected, and subjected to hemagglutinin treatment for later use; (2) a whole blood sample is added to the filter membrane structure for filtration; and (3) the filtered serum or plasma is collected. The filter membrane structure is composed of at least two filtration membranes stacked from top to bottom, and the pore sizes of the filtration membranes stacked gradually decrease from top to bottom, and the areas of the same gradually increase or are equal to each other from top to bottom.

Abstract: In some examples, a system includes a network managed by a service provider and configured to provide access to one or more objects to a set of tenants each having one or more users, the service provider and the set of tenants being part of a set of entities that form a hierarchy, and a controller having access to the network. The controller is configured to obtain data indicative of a set of parameters, where the data indicative of the set of parameters is associated with an owner entity of the set of entities, generate a rule which incorporates the set of parameters, where the rule enables the controller to control access to an object of the one or more objects, and add the rule to a rules database, wherein the rules database is accessible to the controller.

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

Abstract: To improve the accuracy and efficiency of object detection through computer digital image analysis, the detection of some objects can inform the sub-portion of the digital image to which subsequent computer digital image analysis is directed to detect other objects. In such a manner object detection can be made more efficient by limiting the image area of a digital image that is analyzed. Such efficiencies can represent both computational efficiencies and communicational efficiencies arising due to the smaller quantity of digital image data that is analyzed. Additionally, the detection of some objects can render the detection of other objects more accurate by adjusting confidence thresholds based on the detection of those related objects. Relationships between objects can be utilized to inform both the image area on which subsequent object detection is performed and the confidence level of such subsequent object detection.

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: The application describes syringe carriers for medicament delivery devices such as autoinjectors. Methods of assembly are described, including a method of assembling a sub-assembly of a medicament delivery device. The method includes the steps of providing a housing, a syringe carrier and a syringe, wherein the housing extends along a longitudinal axis from a proximal end to a distal end; inserting the syringe carrier into the housing so that the syringe carrier is aligned with the housing along the longitudinal axis and inserting the syringe into the syringe carrier in the longitudinal direction. The syringe carrier remains aligned with the longitudinal axis during insertion of the syringe into the syringe carrier. As the syringe is inserted into the syringe carrier, the syringe rotates from a first position parallel to the longitudinal axis to a second position that is not parallel to the longitudinal axis and then to a third position parallel to the longitudinal axis.

Abstract: A method for semiconductor fabrication includes forming a metal gate surrounded by a first silicon oxide layer, wherein a metallic surface of the metal gate is exposed. The method further includes selectively depositing a silicon nitride layer on the metallic surface and not on the first silicon oxide layer, and depositing a second silicon oxide layer on the first silicon oxide layer and on the silicon nitride layer.

Abstract: The application describes syringe carriers for medicament delivery devices such as autoinjectors. One example concerns a syringe carrier for a syringe with a flange, the syringe carrier having a tubular housing extending along a longitudinal axis from a proximal end to a distal end and a syringe holder attached to the distal end of the tubular housing, wherein the syringe holder is configured to hold the flange of the syringe, and wherein the syringe holder comprises either a c-clip or a screw thread. Other associated syringe carriers, sub-assemblies, medicament delivery devices and corresponding methods are also described.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.