Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Abstract: A computer implemented method manages an ensemble model system to classify records. A number of processor units cluster records into groups of records based on classification predictions generated by base models in the ensemble model system for the records. The number of processor units determines sets of weights for the base models that increase a probability that the base models in the ensemble model system correctly predict the groups of records. Each set of weights in the sets of weights is associated with a group of records in the groups of records.

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: An anti-opening container includes a first box and a second box. The first box includes a first body and a first box section. The first body includes a first side wall. The first box section is formed by the extension of the first side wall. The second box includes a second body, a second box section and an extension section. The second body includes a second base and a second side wall. The second box section is formed by the extension of the second side wall. When the first box and the second box are combined, the first box section is stacked on the second box section. The extension section is formed by the extension of the second side wall, and includes a fastener and a gripping section. When the fastener fits into the first fastening groove, the gripping section is located outside the first fastening groove.

Abstract: An anti-opening container includes a first box and a second box. The first box includes a first body, a first box section and a first gripping section. The first box section is formed by the extension of the first body. The second box includes a second body, a second box section, a second gripping section, an extension section, and a fastener section. The second box section is formed by the extension of the second body. The fastener section is connected to the extension section via a perforated line. The fastener section is embedded in the first box section. When the first gripping section and the second gripping section are displaced in opposite directions, the perforated line breaks, and the first box section and the fastener section are separated from the second box section together to separate the first box and the second box.

Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.

Abstract: A plasma processing apparatus for semiconductor processing includes an injector holder configured to removably mate with a structure defining an interior chamber of a plasma processing apparatus. The injector holder defines a first opening. A sleeve is configured to be received within the first opening, and the sleeve defines a second opening. A gas injector is configured to be received within the second opening of the sleeve.

Abstract: A method for forming a nanosheet device is provided. The method includes epitaxially growing a conformal semiconductor layer from a first stack of semiconductor layers and a second stack of the semiconductor layers. Each of the first and second stack of semiconductor layers includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other. A space between the first and second stacks of semiconductor layers is filled with a dielectric fin. The conformal semiconductor layer and the second semiconductor layers may be removed. A metal gate structure is formed over the first semiconductor layers and filling openings created by removal of the conformal semiconductor layer and the second semiconductor layer. A process may be performed on the metal gate structure to form an isolation between the portions of the metal gate structure being separated by a patterning process.

Abstract: The application describes syringe carriers for medicament delivery devices such as autoinjectors. One example concerns a syringe carrier for a syringe with a flange, the syringe carrier having a tubular housing extending along a longitudinal axis from a proximal end to a distal end and a syringe holder attached to the distal end of the tubular housing, wherein the syringe holder is configured to hold the flange of the syringe, and wherein the syringe holder comprises either a c-clip or a screw thread. Other associated syringe carriers, sub-assemblies, medicament delivery devices and corresponding methods are also described.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: In an approach for post-modeling data visualization and analysis, a processor presents a first visualization of a training dataset in a first plot. Responsive to receiving a selection of a data group of the training dataset to analyze, a processor identifies three or fewer key model features of the data group of the training dataset. A processor ascertains a representative record of each key model feature of the three or fewer key model features using a Local Interpretable Model-Agnostic Explanation technique. A processor presents a second visualization of the three or fewer key model features and the representative record of each key model feature in a second plot.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

Abstract: The present invention provides a system and method for blood pressure measurement, a computer program product using the method, and a computer-readable recording medium thereof. The present invention uses a sensor to measure an electrophysiological signal and establishes a personalized cardiovascular model through a numerical method, and re-establishes the personalized cardiovascular model through an optimization algorithm. Thus, a human physiological parameter generated from the re-established personal cardiovascular model matches the electrophysiological signal. Therefore, the present invention can provide accurate measurement results with the advantage of a small size, and can be applied to telemedicine field.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.

Abstract: A method, computer system, and a computer program product are provided for post-modeling feature evaluation. In one embodiment, at least at least one post model visual output and associated data is obtained that at least includes an individual conditional expectation (ICE) plot and a partial dependence (PDP) plot. Using the associated data and the plots, a Feature Importance (PI) plot is provided. A plurality of features is then determined for each PI, PDP and ICE plots to calculate at least one Interesting Value for each plot. An overall score is also calculated for each plurality of features based on the associated Interesting Values for each PDP, ICE and PI plots. At least one top feature is selected based on said scores. A final plot is then generated at least reflecting the top feature. The final plot combines the PI, PDP and ICE plots together.

Abstract: In various embodiments, method and devices for delivering large cargos (e.g., organelles, chromosomes, bacteria, and the like) into cells are provided. In certain embodiments method of delivering a large cargo into eukaryotic cells, are provided that involve providing eukaryotic cells disposed on one side of a porous membrane; providing the cargo to be delivered in a solution disposed in a reservoir chamber on the opposite side of the porous membrane; and applying pressure to the reservoir chamber sufficient to pass the cargo through pores comprising said porous membrane wherein said cargo passes through cell membranes and into the cells.

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.