Abstract: A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.

Abstract: The application describes syringe carriers for medicament delivery devices such as autoinjectors. In particular, a medicament delivery device sub-assembly is described. The medicament delivery device sub-assembly has a housing extending along a longitudinal axis from a proximal end to a distal end, the housing has a tubular section with an internal surface facing towards the axis and an external surface facing away from the axis, wherein the housing has an aperture extending through the tubular section from the internal surface to the external surface; and a housing cover assembly attached in the aperture of the housing, the housing cover assembly being configured to secure a syringe in place relative to the housing.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, an interlayer dielectric (ILD), and a conductive layer. The ILD is disposed on the substrate. The conductive layer is disposed on the substrate and spaced apart from the ILD by an air gap. The ILD is tapered toward the substrate.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A transmission device for lifting a sickbed contains a first casing, a second casing, a power input assembly, a power output assembly, and multiple screw elements. The first casing includes a first rotatable connection portion, a second rotatable connection portion, a first space, and multiple locking orifices. The second casing includes a third rotatable connection portion, a fourth rotatable connection portion, a second space, and multiple coupling orifices. The power input assembly includes an input shaft and a first bevel gear. The power output assembly includes an output shaft and a second bevel gear. The multiple screw elements are inserted through the multiple coupling orifices of the second casing to screw with the multiple locking orifices of the first casing.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.

Abstract: A color wheel module and a projector are provided. The projector includes the color wheel module, and the color wheel module includes a disk, an isolation framework, an assembly member, and an adhesive filler. The disk is configured to rotate around an axis. The isolation framework and the assembly member are disposed on the disk. The isolation framework is located between the disk and the assembly member. An air layer is formed between the assembly member and the isolation framework. The adhesive filler is disposed on the assembly member.

Abstract: A color wheel module and a projector are provided. The projector includes the color wheel module, and the color wheel module includes a disk, an isolation framework, an assembly member, and a colloidal filler. The disk is configured to rotate around an axis. The isolation framework and the assembly member are disposed on the disk. The isolation framework is located between the disk and the assembly member. An air layer is formed between the disk, the assembly member and the isolation framework. The colloidal filler is disposed on the assembly member.

Abstract: An integrated circuit includes a semiconductor nanostructure transistor. The semiconductor nanostructure transistor includes a plurality of semiconductor nanostructures corresponding to channel regions conductor Nanostructure transistor. A gate metal surrounds the semiconductor nanostructures. The gate metal has differing gate length dimension above the semiconductor nanostructures compared to the gate length between the semiconductor nanostructures.

Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

Abstract: The present disclosure provides a fixed-position defect doping method for a micro-nanostructure based on a self-alignment process, including: S1, sequentially forming a sacrificial layer and a photoresist layer on a surface of a crystal substrate; S2, performing a lithography on the photoresist layer to form a mask hole according to a micro-nano pattern; S3, performing an isotropic etching on the sacrificial layer through the mask hole, and amplifying the micro-nano pattern to the sacrificial layer; S4, performing an ion implantation doping on an exposed crystal surface below the mask hole; S5, removing the photoresist layer, and depositing a mask material; S6, removing the sacrificial layer, and transferring a micro-nano amplified pattern in the sacrificial layer to a mask material pattern; and S7, etching an exposed crystal surface, and removing the mask material on the surface and forming a specific defect by annealing.

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.

Abstract: A plasma processing apparatus for semiconductor processing includes an injector holder configured to removably mate with a structure defining an interior chamber of a plasma processing apparatus. The injector holder defines a first opening. A sleeve is configured to be received within the first opening, and the sleeve defines a second opening. A gas injector is configured to be received within the second opening of the sleeve.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: The present invention provides uses of an andrographolide derivative in preparation of a medicament for preventing and treating inflammatory bowel disease. The andrographolide derivative AL-1 has the mechanisms, for the treatment of ulcerative colitis, of scavenging of free radicals, inhibition of NF-?B signaling pathway activation and COX-2 expression, activation of PPAR-? expression, and thus can prevent the transcription and expression of inflammatory-related genes to improve the conditions of inflammation. AL-1 can be used as a medicine for the treatment of inflammatory bowel disease and can be formulated to various dosage forms with a pharmaceutically acceptable carrier.

Abstract: Detecting anomalous data by applying a plurality of models to a data set to yield detection results including anomalous data, applying evaluation methods to the detection results for each of the plurality of models, determining a combined score for the detection results according to the evaluation methods, determining a combined score threshold, and defining a set of detected anomalies according to the combined score and the combined score threshold.