Abstract: Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Abstract: Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Abstract: In various embodiments a circuit is provided which may include a node at which a circuit potential may be provided; an alternating voltage providing circuit configured to provide a DC current free alternating voltage; a rectifier coupled to the alternating voltage providing circuit, the rectifier including a first rectifier terminal and a second rectifier terminal, wherein the first rectifier terminal or the second rectifier terminal may be coupled to the node; and a first output terminal and a second output terminal, wherein the first output terminal may be coupled to the first rectifier terminal to provide a first potential and wherein the second output terminal may be coupled to the second rectifier terminal to provide a second potential different from the first potential, the difference between the first potential and the second potential defining an output voltage, wherein the output voltage may be constant independent of the circuit potential.

Abstract: Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

Abstract: A method is disclosed. An analog signal is sampled to form a sample value using a sample and hold circuit. The sample value is converted to form a first digital result. The sample value is converted to form a second digital result.

Abstract: A precharge sample-and-hold circuit is provided that has an input terminal, a reference voltage terminal and an output terminal. The circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal. The sampling capacitance is configured to provide the sample voltage when the sample-and-hold circuit is in a holding mode. The circuit also has a cancellation capacitance. An analog/digital converter is provided that uses the precharge sample-and-hold circuit. A method to operate the precharge sample-and-hold circuit is also provided.

Abstract: A multi voltage sensor system includes one or more charge pumps, a sensor bridge and readout circuitry. The one or more charge pumps are configured to provide a high voltage. The sensor bridge is biased by the high voltage and is configured to provide sensor values. The readout circuitry includes only low voltage components. The readout circuitry is configured to receive the sensor values.

Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.

Abstract: A method is disclosed. An analog signal is sampled to form a sample value using a sample and hold circuit. The sample value is converted to form a first digital result. The sample value is converted to form a second digital result.

Abstract: Disclosed herein are embodiments of a pre-charge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when the sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a pre-charge sample-and-hold circuit and of methods to operate a pre-charge sample-and-hold circuit in an analog/digital converter are also disclosed.

Abstract: A method and an apparatus for a shunt measurement are provided. In one embodiment a measurement unit includes an input for a source device, the source device configured to provide a first analog voltage level to be measured in a first operating mode of the source device and a second analog voltage level to be measured in a second operating mode of the source device, a control input configured to detect the operating mode of the source device and an input stage configured to minimize a reaction time of the measurement unit after a change of the operating mode of the source device.

Abstract: In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided.

Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.

Abstract: A semiconductor chip with a built-in-self-test circuit including a first analog-to-digital converter (ADC) configured to convert an analog input voltage signal received at its input into a digital output voltage signal that characterizes the first ADC; and a second ADC coupled to the input of the first ADC and configured to convert the analog input voltage signal received at its input to a digital feedback voltage signal, wherein the analog input voltage signal is generated based on the digital feedback signal.

Abstract: This disclosure describes techniques for measuring the resistance of a component with measurement circuitry that is electrically coupled to the component via one or more electrical conductors (e.g., one or more bond wires). The resistance measurement techniques of this disclosure may measure a resistance of an electrical conductor, and generate a value indicative of a resistance of a component other than the electrical conductor based on the measured resistance of the electrical conductor. The electrical conductor for which the resistance is measured may be the same as or different than one or more of the electrical conductors that the couple the measurement circuitry to the component to be measured. Using an electrical conductor resistance measurement to determine the resistance of a component may improve the accuracy of the resistance measurement for the component.

Abstract: A semiconductor chip with a built-in-self-test circuit including a first analog-to-digital converter (ADC) configured to convert an analog input voltage signal received at its input into a digital output voltage signal that characterizes the first ADC; and a second ADC coupled to the input of the first ADC and configured to convert the analog input voltage signal received at its input to a digital feedback voltage signal, wherein the analog input voltage signal is generated based on the digital feedback signal.

Abstract: In various embodiments a circuit is provided which may include a node at which a circuit potential may be provided; an alternating voltage providing circuit configured to provide a DC current free alternating voltage; a rectifier coupled to the alternating voltage providing circuit, the rectifier including a first rectifier terminal and a second rectifier terminal, wherein the first rectifier terminal or the second rectifier terminal may be coupled to the node; and a first output terminal and a second output terminal, wherein the first output terminal may be coupled to the first rectifier terminal to provide a first potential and wherein the second output terminal may be coupled to the second rectifier terminal to provide a second potential different from the first potential, the difference between the first potential and the second potential defining an output voltage, wherein the output voltage may be constant independent of the circuit potential.

Abstract: In various embodiments a circuit is provided which may include a node at which a circuit potential may be provided; an alternating voltage providing circuit configured to provide a DC current free alternating voltage; a rectifier coupled to the alternating voltage providing circuit, the rectifier including a first rectifier terminal and a second rectifier terminal, wherein the first rectifier terminal or the second rectifier terminal may be coupled to the node; and a first output terminal and a second output terminal, wherein the first output terminal may be coupled to the first rectifier terminal to provide a first potential and wherein the second output terminal may be coupled to the second rectifier terminal to provide a second potential different from the first potential, the difference between the first potential and the second potential defining an output voltage, wherein the output voltage may be constant independent of the circuit potential.

Abstract: A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor. The first load terminals of the load and the sense transistors are at respective floating electric potentials. A floating sense circuit coupled between the load terminals of sense transistor and load transistor, at least in one mode of operation the sense circuit receives the sense current and provides a floating signal representing the sense current. A non-floating measurement circuit is coupled to the sense circuit via a DC decoupling capacitor for transferring the floating signal representing the sense current to the non-floating measurement circuit.