Patents by Inventor Peter Hazucha

Peter Hazucha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160170456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: September 25, 2012
    Publication date: June 16, 2016
    Applicant: INTEL CORPORATION
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Patent number: 9124174
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek K. De, Tanay Karnik
  • Patent number: 8994344
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Tanay Karnik, Vivek K. De, Fabrice Paillet
  • Patent number: 8773233
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Patent number: 8710869
    Abstract: A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Tsung-Hao Chen, Tanay Karnik, Chung-Ping Chen
  • Patent number: 8694816
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: April 8, 2014
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Publication number: 20140089687
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Patent number: 8629667
    Abstract: Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner
  • Publication number: 20130271105
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek K. De, Tanay Karnik
  • Patent number: 8513750
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20130182365
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Application
    Filed: February 4, 2013
    Publication date: July 18, 2013
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Patent number: 8482552
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Patent number: 8471667
    Abstract: Some embodiments include a die having a transformer. The transformer includes windings formed from a set of lines, such that no two lines belonging to any one winding are nearest neighbors. The lines are formed within one layer on the die. Other embodiments are described.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • Publication number: 20130113444
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 9, 2013
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Tanay Karnik, Vivek K. De, Fabrice Paillet
  • Patent number: 8373074
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Patent number: 8368501
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Patent number: 8361594
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 8358112
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: January 22, 2013
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • Patent number: 8288846
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Publication number: 20120194245
    Abstract: Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 2, 2012
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner