Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.

Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.

Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.

Abstract: In general, in one aspect, the disclosure describes a semiconductor device that includes a functional circuit and a dc-to-dc power converter. The power converter converts, regulates, and filters a DC input voltage to produce a DC output voltage and provides the DC output voltage to the functional circuit. The dc-to-dc power converter has an operating frequency above 10 MHz.

Abstract: A multi-phase transformer is provided that includes a first layer having at least a first planar wire and a second planar wire and a second layer formed on the first layer and having at least a third planar wire and a fourth planar wires. At least the first planar wire and the second planar wire of the first layer to form two transformers with at least two planar wires of the second layer. The multi-phase transformer may also include a coupling device to couple one end of the planar wires of the first layer with one of the planar wires of the second layer.

Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.

Abstract: One disclosed system includes a plurality of current sink elements coupled between a power supply and a reference potential. A plurality of multiplexers are configured to enable the current sink elements to sink current, and a plurality of selection inputs are configured to control the state of the multiplexers.

Abstract: A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.

Abstract: A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.

Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A transistor may operate as a sleep transistor or as a regulator.

Abstract: A method is described that comprises flowing current from one region of a coil to another region of the coil. The flowing induces—through flux linkage—a voltage across a second coil. A second current substantially does not flow through the second coil. The method also includes measuring the current with a first voltage at the another region of the coil and a second voltage at the second coil.

Abstract: A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.

Abstract: A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.

Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A method and apparatus for multi-phase transformers are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors. In one embodiment, each primary inductor is coupled to one of N input nodes and a common output node. The transformer further includes N?1 secondary inductors coupled in series between one input node and the common output node. In one embodiment, the N?1 secondary inductors are arranged to couple energy from N?1 of the primary inductors to provide a common node voltage as an average of N input node voltages, wherein N is an integer greater than two. Other embodiments are described and claimed.

Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator/converter die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.