Patents by Inventor Peter Hazucha

Peter Hazucha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080100371
    Abstract: Some embodiments disclosed herein provide dual rail generators to provide a high and a low supply rail.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon
  • Patent number: 7358770
    Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 15, 2008
    Inventors: Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Vivek K. De
  • Publication number: 20080001701
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20080001699
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20080001698
    Abstract: Multiple-inductor embodiments for use in substrates are provided herein.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Peter Hazucha, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Publication number: 20080003760
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20080002380
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Publication number: 20080003699
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 7315463
    Abstract: A method and apparatus for multi-phase transformers are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors. In one embodiment, each primary inductor is coupled to one of N input nodes and a common output node. The transformer further includes N?1 secondary inductors coupled in series between one input node and the common output node. In one embodiment, the N?1 secondary inductors are arranged to couple energy from N?1 of the primary inductors to provide a common node voltage as an average of N input node voltages, wherein N is an integer greater than two. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 1, 2008
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Donald S. Gardner, Vivek K. De, Tanay Karnik
  • Publication number: 20070260848
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: July 3, 2007
    Publication date: November 8, 2007
    Inventors: Siva Narendra, James Tschanz, Howard Wilson, Donald Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek De, Shekhar Borkar
  • Patent number: 7274181
    Abstract: Droop-control circuitry of a multiphase power converter determines when multiphase switching signals are concurrently at either a high or low state and temporarily clamps the output of the power converter to either a high or low voltage level in response thereto.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek K. De, Tanay Karnik
  • Patent number: 7274250
    Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Sung T. Moon, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Vivek De
  • Patent number: 7265607
    Abstract: A device comprises an active-pull-up stage and an active-pull-down stage. The device receives at least one reference voltage and provides an regulated output voltage to at least one load. The active-pull-up and active-pull-down stages are adapted to source or sink a current delivered to or received from the at least one load to regulate the output voltage provided to the at least one load. Other embodiments and methods are also claimed and described.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 4, 2007
    Assignee: Intel Corporation
    Inventors: Saravanan Rajapandian, Peter Hazucha, Tanay Karnik
  • Patent number: 7262632
    Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Gerhard Schrom, Tanay Karnik, Vivek K De
  • Patent number: 7247930
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Patent number: 7224203
    Abstract: In an embodiment, a switched capacitor transformer transfers a differential reference voltage at its input ports to its output ports, where a capacitor is switched so that the capacitor is coupled to the input ports during a first portion of a cycle of operation and then coupled to the output ports during a second portion of the cycle of operation, where the first and second portions of the cycle of operation are non-overlapping. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Tanay Karnik
  • Patent number: 7212021
    Abstract: A method for designing and testing on-die power supply, power distribution, and noise suppression techniques for integrated circuits such as microprocessors is described. A network of time varying loads is distributed along the power supply grid to facilitate testing of new power supplies and grids and noise suppression techniques before design of the chip is completed. Several programmable current sinks are described for presenting loads according to a preferred test-waveform current. Transient, including droop detection, and static testing is easily performed using the described methods and circuitry.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Tanay Karnik, Peter Hazucha
  • Patent number: 7208963
    Abstract: A method and apparatus is described according to various embodiments, for flowing current from one region of a coil to another region of the coil. The flowing induces—through flux linkage —a voltage across a second coil. A second current substantially does not flow though the second coil. The method and apparatus also includes measuring the current with the voltage between the two coils.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Donald S. Gardner, Vivek K. De, Tanay Karnik
  • Patent number: 7199617
    Abstract: A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode stage may receive a first voltage and may be connected to the input stage. The cross-coupled stage may be adapted to isolate the first voltage and may be connected to the cascode stage. The output stage may receive a second voltage, provide an output, and be connected to the cross-coupled stage. The cascode stage may be adapted to provide the first voltage as the output when the logic input is a first value and provide the second voltage as the output when the logic input is a second value. Other embodiments are also claimed and described.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Peter Hazucha, Stephen Tang, Vivek De
  • Publication number: 20070052446
    Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
    Type: Application
    Filed: March 21, 2006
    Publication date: March 8, 2007
    Inventors: Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Vivek De