Patents by Inventor Peter Hazucha

Peter Hazucha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Signal generating circuit
    Patent number: 7602257
    Abstract: A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • SLOTTED MAGNETIC MATERIAL FOR INTEGRATED CIRCUIT INDUCTORS
    Publication number: 20090207576
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 20, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power Delivery System
    Publication number: 20090199033
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Application
    Filed: January 20, 2009
    Publication date: August 6, 2009
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER
    Publication number: 20090174377
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: March 16, 2009
    Publication date: July 9, 2009
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20090166804
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Grounding of magnetic cores
    Patent number: 7538653
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • METHODS OF FORMING MAGNETIC VIAS TO MAXIMIZE INDUCTANCE IN INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY
    Publication number: 20090117325
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power delivery system in which power supply and load exchange power consumption measurements via digital bus
    Patent number: 7523337
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: April 21, 2009
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Slotted magnetic material for integrated circuit inductors
    Patent number: 7518481
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Multiphase transformer for a multiphase DC-DC converter
    Patent number: 7504808
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • IC with fully integrated DC-to-DC power converter
    Patent number: 7482792
    Abstract: In general, in one aspect, the disclosure describes a semiconductor device that includes a functional circuit and a dc-to-dc power converter. The power converter converts, regulates, and filters a DC input voltage to produce a DC output voltage and provides the DC output voltage to the functional circuit. The dc-to-dc power converter has an operating frequency above 10 MHz.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: January 27, 2009
    Assignee: Intel Corporation
    Inventors: Edward Burton, Peter Hazucha, Gerhard Schrom, Rajesh Kumar, Shekhar Y. Borkar
  • CONTROL OF EDDY CURRENTS IN MAGNETIC VIAS FOR INDUCTORS AND TRANSFORMERS IN INTEGRATED CIRCUITS
    Publication number: 20080290980
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Application
    Filed: August 6, 2008
    Publication date: November 27, 2008
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power transformer
    Patent number: 7436277
    Abstract: A multi-phase transformer is provided that includes a first layer having at least a first planar wire and a second planar wire and a second layer formed on the first layer and having at least a third planar wire and a fourth planar wires. At least the first planar wire and the second planar wire of the first layer to form two transformers with at least two planar wires of the second layer. The multi-phase transformer may also include a coupling device to couple one end of the planar wires of the first layer with one of the planar wires of the second layer.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Gerhard Schrom, Weimin Shi, Edward Burton, Trang Nguyen, Mary Bloechel, legal representative, Tanay Karnik, Bradley Bloechel
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20080238596
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • COMPONENTS WITH ON-DIE MAGNETIC CORES
    Publication number: 20080238602
    Abstract: An apparatus may include a first magnetic layer, a second magnetic layer, and a conductive pattern. The conductive pattern is at a third layer between the first and second magnetic layers. Moreover, one or more magnetic vias connect the first and second magnetic layers. The magnetic layers and vias may operate as ferromagnetic cores or shields. Further they may be integrated on a chip (on-die magnetics). The apparatus may be included in inductors, transformers, transmission lines, and so forth.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Control of eddy currents in magnetic vias for inductors and transformers in integrated circuits
    Patent number: 7423508
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Stepwise drivers for DC/DC converters
    Patent number: 7394298
    Abstract: Stepwise drivers for DC/DC converters are described herein. In one embodiment, a stepwise driver is provided to charge or discharge a gate capacitance of a power switch of a DC/DC converter. In a particular embodiment, a stepwise driver example includes multiple switching elements to sequentially switch to charge a gate capacitance of a power switch of a DC/DC converter from a first voltage to a second voltage in multiple steps. Other methods and apparatuses are also described.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Sung T. Moon, Gerhard Schrom, Tanay Karnik, Vivek De
  • PULSE WIDTH MODULATOR
    Publication number: 20080143408
    Abstract: In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner
  • Signal generating circuit
    Publication number: 20080143407
    Abstract: Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Gerhard Schrom, Dinesh Somasekhar, Fabrice Paillet, Peter Hazucha, Sung Tae Moon, Tanay Karnik
  • Voltage regulation using digital voltage control
    Patent number: 7372382
    Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Saravanan Rajapandian, Gerhard Schrom, Tanay Karnik, Vivek De