Abstract: A DC to DC switching power converter includes switching elements having capacitive gate control inputs, an energy storage element and driver circuitry. The driver circuitry generates a partial-swing switching signal to at least one of switching elements to achieve efficiency improvement by reducing the energy required to charge and discharge the capacitance of the gate control input. In one embodiment, the switching power converter is fabricated on a semiconductor die to generate an output voltage to one or more functional unit blocks on the die. Several power converters can be combined to form an on-die multiphase power converter.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: Embodiments of the present invention relate to independently switched inductors in a voltage converter. Each voltage transforming inductor of a voltage converter may be designated a switch or bridge at each opposing terminal. The function of these switches is to periodically reverse the polarity of voltage across the inductors. By configuring independently switched inductors in series, the frustration of voltage tolerance limitations of the switches is mitigated.

Abstract: According to some embodiments, a plurality of single-phase hysteretic converters operate in accordance with associated synchronization signals.

Abstract: According to some embodiments, non-overlapping clocks are to be generated.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: A voltage regulator for generating a constant output voltage. The voltage regulator includes an output stage having an internal feedback loop connected to control a current delivered to or received from a load to maintain the output voltage substantially constant relative to an internal reference voltage. The voltage regulator further includes a second feedback loop connected to control the internal reference voltage to cause the output voltage to track an external reference voltage.

Abstract: A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.

Abstract: A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.

Abstract: A method for designing and testing on-die power supply, power distribution, and noise suppression techniques for integrated circuits such as microprocessors is described. A network of time varying loads is distributed along the power supply grid to facilitate testing of new power supplies and grids and noise suppression techniques before design of the chip is completed. Several programmable current sinks are described for presenting loads according to a preferred test-waveform current. Transient, including droop detection, and static testing is easily performed using the described methods and circuitry.

Abstract: A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.

Abstract: An on-die multiple phase power converter reduces output voltage ripple and reduces input current ripple while allowing for higher input voltage and reduced input current to a circuit board. The on-die multiple phase power converter also allows for more than one supply voltage on a die. The converter includes a plurality of single phase switching blocks and a clock signal phase generator. The single phase switching blocks receive phase-shifted clock signals from the clock signal phase generator and provide an output voltage. The output currents of the single phase switching blocks may combine to form a single output to provide current to one or more functional unit blocks on the semiconductor die. One or more or the single phase switching elements may be combined to provide current to one or more functional unit blocks on the semiconductor die.

Abstract: An on-die multiple phase power converter reduces output voltage ripple and reduces input current ripple while allowing for higher input voltage and reduced input current to a circuit board. The on-die multiple phase power converter also allows for more than one supply voltage on a die. The converter includes a plurality of single phase switching blocks and a clock signal phase generator. The single phase switching blocks receive phase-shifted clock signals from the clock signal phase generator and provide an output voltage. The output currents of the single phase switching blocks may combine to form a single output to provide current to one or more functional unit blocks on the semiconductor die. One or more or the single phase switching elements may be combined to provide current to one or more functional unit blocks on the semiconductor die.

Abstract: A DC-to-DC switching power converter includes switching elements having capacitive gate control inputs, an energy storage element and driver circuitry. Improved efficiency is achieved using adiabatic buffers to drive MOSFET switching elements with stepped switching signals. Substantially equal rise and fall times are achieved. In one embodiment, the switching power converter is fabricated on a semiconductor die to generate an output voltage to one or more functional unit blocks on the die.

Abstract: A DC-to-DC switching power converter includes switching elements having capacitive gate control inputs, an energy storage element and driver circuitry. Improved efficiency is achieved using adiabatic buffers to drive MOSFET switching elements with stepped switching signals. Substantially equal rise and fall times are achieved. In one embodiment, the switching power converter is fabricated on a semiconductor die to generate an output voltage to one or more functional unit blocks on the die.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.