Abstract: A method for determining a plant growth curve includes obtaining color images and depth images of a plant to be detected at different time points, performing alignment processing on each color image and each depth image to obtain an alignment image, detecting the color image through a pre-trained target detection model to obtain a target bounding box, calculating an area ratio of the target bounding box in the color image, determining a depth value of all pixel points in the target boundary frame according to the aligned image, performing denoising processing on each depth value to obtain a target depth value, generating a first growth curve of the plant to be detected according to the target depth values and corresponding time points, and generating a second growth curve of the plant to be detected according to the area ratios and the corresponding time points.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A method for determining a height of a plant, an electronic device, and a storage medium are disclosed. In the method, a target image is obtained by mapping an obtained color image with an obtained depth image. The electronic device processes the color image by using a pre-trained mobilenet-ssd network, obtains a detection box appearance of the plant, and extracts target contours of the plant to be detected from the detection box. The electronic device determines a depth value of each of pixel points in the target contour according to the target image. Target depth values are obtained by performing a de-noising on depth values of the pixel points, and a height of the plant to be detected is determined according to the target depth value. The method improves accuracy of height determination of a plant.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.

Abstract: Provided are a database processing method and apparatus, and a computer readable storage medium. The database processing method comprises: after a lock wait is generated, writing lock wait related information into a lock wait log.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.

Abstract: In some examples, the disclosure describes a device that includes a docking station and a processor. The processor may determine that an error condition involving disconnection of a computing device from the docking station couplable to the computing device has occurred and receive, responsive to the determination, a signal indicative of performance of an operation to re-establish communication with the docking station. The processor may further perform, responsive to receipt of the signal, the operation to re-establish communication with the docking station.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: Complex concentrated alloys include five or more elements, at least one of which is ruthenium. Example complex concentrated alloys can include nickel and chromium, iron, ruthenium, molybdenum, and/or tungsten. Example complex concentrated alloys have single phase microstructure of face centered cubic (FCC) and can be homogenous. Example complex concentrated alloys can exhibit improved corrosion resistance.

Abstract: Adaptive power management of a computing device is provided such that computer power can be dynamically allocated and adjusted among CPU and other power consuming peripherals based on the power usage pattern of individual users. Power overuse (surge and/or agency) events occurred during a time period (e.g., a week) are recorded in a database. By analyzing the recorded power overuse events, the computing device can be operated under a customized power budget profile learned from the user's power usage pattern, allowing different weight to different power consuming components, so as to optimize the performance of the computing device based on the usage scenario of different users at different time.

Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.

Abstract: A black body radiation device is provided, which can be used as a benchmark heat source for “thermal imager” temperature detection device. The black body radiation device includes: a heat source module comprising a heater and a temperature equalizing plate, wherein the temperature equalizing plate contacts the heater; a temperature control module connected to the heater to control the heater, thereby keeping the temperature equalizing plate at a predetermined temperature; and a housing configured to accommodate the heat source module and the temperature control module, the housing having an opening, wherein the opening is configured to expose the temperature equalizing plate.

Abstract: A semiconductor device includes a substrate, at least one heterojunction bipolar transistor including a semiconductor unit and an electrode unit, an insulation unit, and a heat dissipation unit. The insulation unit covers the substrate and the heterojunction bipolar transistor such that a collector electrode, a base electrode and an emitter electrode of the electrode unit are electrically isolated from one another. The insulation unit is formed with an opening to expose an electrode wire of the emitter electrode. The heat dissipation unit covers the electrode wire and is made of an electrically conductive and heat dissipating material, and has a thickness that is not less than 3 ?m.

Abstract: The disclosure is directed to an ex vivo cell culture system and methods of using the cell culture system to identify potential therapeutic agents for the treatment of leukemia or lymphoma, such as chronic lymphocytic leukemia (CLL). The ex vivo culture system comprises (a) a first cell culture comprising bone marrow stromal cells (BMSC) which express one or more exogenous cell signaling molecules; (b) a second cell culture comprising leukemia or lymphoma cells isolated from a human; and optionally (c) one or more soluble cell signaling molecules.

Abstract: A pad structure includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located above the substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and between the conductive layer and the pad layer. The conductive layer includes a number of effective blocks, and a proportion of a block area of a block of the effective blocks to a total block area of the effective blocks ranges between 40%-50%. The block has at least one hollow portion, wherein the hollow portion has a total hollow area, and a ratio of the total hollow area to the block area ranged between 0.1 and 0.5.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.