Patents by Inventor Pin Lu

Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002272
    Abstract: A method for classifying cells densities by cell images being input into artificial computer intelligence obtains positional information of all central points of all groups of first encoding features generated when training a model of convolutional neural network and ranges of densities of images of biological cells represented by different central points. The method inputs a test image of the biological cells into a trained model of the convolutional neural network to encode the test image, to obtain a second encoding feature. The method also determines a central point nearest to the second encoding feature according to the positional information. The method determines a range of densities of the test image according to the ranges of densities of the images represented by different central points and the central point nearest to the second encoding feature. An electronic device and a non-transitory storage medium are also disclosed.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: June 4, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wan-Jhen Lee, Chih-Te Lu, Chin-Pin Kuo
  • Publication number: 20240167832
    Abstract: A driving route planning method applied to an electronic device is provided. The method includes acquiring an image when a vehicle is driving. Target route information is obtained by inputting the image into a target route planning model. Once a first embedding vector of the target route information is extracted, a driving route corresponding to a driving style is obtained by inputting the first embedding vector into a target driving style model.
    Type: Application
    Filed: February 14, 2023
    Publication date: May 23, 2024
    Inventors: JUNG-HAO YANG, CHIN-PIN KUO, CHIH-TE LU
  • Patent number: 11972562
    Abstract: A method for determining a plant growth curve includes obtaining color images and depth images of a plant to be detected at different time points, performing alignment processing on each color image and each depth image to obtain an alignment image, detecting the color image through a pre-trained target detection model to obtain a target bounding box, calculating an area ratio of the target bounding box in the color image, determining a depth value of all pixel points in the target boundary frame according to the aligned image, performing denoising processing on each depth value to obtain a target depth value, generating a first growth curve of the plant to be detected according to the target depth values and corresponding time points, and generating a second growth curve of the plant to be detected according to the area ratios and the corresponding time points.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 30, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Te Lu, Chin-Pin Kuo, Tzu-Chen Lin
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11954875
    Abstract: A method for determining a height of a plant, an electronic device, and a storage medium are disclosed. In the method, a target image is obtained by mapping an obtained color image with an obtained depth image. The electronic device processes the color image by using a pre-trained mobilenet-ssd network, obtains a detection box appearance of the plant, and extracts target contours of the plant to be detected from the detection box. The electronic device determines a depth value of each of pixel points in the target contour according to the target image. Target depth values are obtained by performing a de-noising on depth values of the pixel points, and a height of the plant to be detected is determined according to the target depth value. The method improves accuracy of height determination of a plant.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 9, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tzu-Chen Lin, Chih-Te Lu, Chin-Pin Kuo
  • Publication number: 20240113061
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11948800
    Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 11928132
    Abstract: Provided are a database processing method and apparatus, and a computer readable storage medium. The database processing method comprises: after a lock wait is generated, writing lock wait related information into a lock wait log.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Pin Lin, Yan Ding, Qinyuan Lu, Chen Qi, Yifang Yu, Pei Zhao
  • Patent number: 11895841
    Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 6, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Pei-Ci Jhang, Chi-Pin Lu
  • Publication number: 20230403852
    Abstract: An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Chi-Pin LU, Pei-Ci JHANG, Masaru NAKAMICHI, Ling-Wuu YANG, Kuang-Chao CHEN
  • Publication number: 20230129307
    Abstract: In some examples, the disclosure describes a device that includes a docking station and a processor. The processor may determine that an error condition involving disconnection of a computing device from the docking station couplable to the computing device has occurred and receive, responsive to the determination, a signal indicative of performance of an operation to re-establish communication with the docking station. The processor may further perform, responsive to receipt of the signal, the operation to re-establish communication with the docking station.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Inventors: Chun Chang, Ming-Hong Lee, Anand Kulkarni, Li-Pin Lu, Rajesh Shah
  • Publication number: 20230100464
    Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Pei-Ci JHANG, Chi-Pin LU
  • Publication number: 20230009981
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Patent number: 11499212
    Abstract: Complex concentrated alloys include five or more elements, at least one of which is ruthenium. Example complex concentrated alloys can include nickel and chromium, iron, ruthenium, molybdenum, and/or tungsten. Example complex concentrated alloys have single phase microstructure of face centered cubic (FCC) and can be homogenous. Example complex concentrated alloys can exhibit improved corrosion resistance.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 15, 2022
    Assignee: QUESTEK INNOVATIONS LLC
    Inventors: Pin Lu, James Saal, Greg Olson
  • Publication number: 20220342469
    Abstract: Adaptive power management of a computing device is provided such that computer power can be dynamically allocated and adjusted among CPU and other power consuming peripherals based on the power usage pattern of individual users. Power overuse (surge and/or agency) events occurred during a time period (e.g., a week) are recorded in a database. By analyzing the recorded power overuse events, the computing device can be operated under a customized power budget profile learned from the user's power usage pattern, allowing different weight to different power consuming components, so as to optimize the performance of the computing device based on the usage scenario of different users at different time.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chu-Ching CHEN, Ming-Hong LEE, Chun CHANG, Li-Pin LU
  • Patent number: 11457850
    Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 4, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hung-Pin Lu, Po-Tsang Huang, Wei Hwang
  • Publication number: 20220034722
    Abstract: A black body radiation device is provided, which can be used as a benchmark heat source for “thermal imager” temperature detection device. The black body radiation device includes: a heat source module comprising a heater and a temperature equalizing plate, wherein the temperature equalizing plate contacts the heater; a temperature control module connected to the heater to control the heater, thereby keeping the temperature equalizing plate at a predetermined temperature; and a housing configured to accommodate the heat source module and the temperature control module, the housing having an opening, wherein the opening is configured to expose the temperature equalizing plate.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 3, 2022
    Inventors: Hsiang-Pin LU, Chia-Chia HUANG, Chao-Chou YUEH, Chia-Jung HSU
  • Publication number: 20210272877
    Abstract: A semiconductor device includes a substrate, at least one heterojunction bipolar transistor including a semiconductor unit and an electrode unit, an insulation unit, and a heat dissipation unit. The insulation unit covers the substrate and the heterojunction bipolar transistor such that a collector electrode, a base electrode and an emitter electrode of the electrode unit are electrically isolated from one another. The insulation unit is formed with an opening to expose an electrode wire of the emitter electrode. The heat dissipation unit covers the electrode wire and is made of an electrically conductive and heat dissipating material, and has a thickness that is not less than 3 ?m.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 2, 2021
    Inventors: You-Min CHI, Kuo-Chun HUANG, Kun-Mu HSIEH, Yu-Chen CHIU, Chi-Chun LIN, Wen-Pin LU, Chao-Hung CHEN
  • Publication number: 20210228646
    Abstract: The disclosure is directed to an ex vivo cell culture system and methods of using the cell culture system to identify potential therapeutic agents for the treatment of leukemia or lymphoma, such as chronic lymphocytic leukemia (CLL). The ex vivo culture system comprises (a) a first cell culture comprising bone marrow stromal cells (BMSC) which express one or more exogenous cell signaling molecules; (b) a second cell culture comprising leukemia or lymphoma cells isolated from a human; and optionally (c) one or more soluble cell signaling molecules.
    Type: Application
    Filed: April 30, 2019
    Publication date: July 29, 2021
    Inventors: Y. Lynn Wang, Pin Lu
  • Publication number: 20210104477
    Abstract: A pad structure includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located above the substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and between the conductive layer and the pad layer. The conductive layer includes a number of effective blocks, and a proportion of a block area of a block of the effective blocks to a total block area of the effective blocks ranges between 40%-50%. The block has at least one hollow portion, wherein the hollow portion has a total hollow area, and a ratio of the total hollow area to the block area ranged between 0.1 and 0.5.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: Chih-Ching Eric SHIH, Hung-Chi CHEN, Li-Kuang KUO, Wen-Pin LU