Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.

Abstract: In some examples, the disclosure describes a device that includes a docking station and a processor. The processor may determine that an error condition involving disconnection of a computing device from the docking station couplable to the computing device has occurred and receive, responsive to the determination, a signal indicative of performance of an operation to re-establish communication with the docking station. The processor may further perform, responsive to receipt of the signal, the operation to re-establish communication with the docking station.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: Complex concentrated alloys include five or more elements, at least one of which is ruthenium. Example complex concentrated alloys can include nickel and chromium, iron, ruthenium, molybdenum, and/or tungsten. Example complex concentrated alloys have single phase microstructure of face centered cubic (FCC) and can be homogenous. Example complex concentrated alloys can exhibit improved corrosion resistance.

Abstract: Adaptive power management of a computing device is provided such that computer power can be dynamically allocated and adjusted among CPU and other power consuming peripherals based on the power usage pattern of individual users. Power overuse (surge and/or agency) events occurred during a time period (e.g., a week) are recorded in a database. By analyzing the recorded power overuse events, the computing device can be operated under a customized power budget profile learned from the user's power usage pattern, allowing different weight to different power consuming components, so as to optimize the performance of the computing device based on the usage scenario of different users at different time.

Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.

Abstract: A black body radiation device is provided, which can be used as a benchmark heat source for “thermal imager” temperature detection device. The black body radiation device includes: a heat source module comprising a heater and a temperature equalizing plate, wherein the temperature equalizing plate contacts the heater; a temperature control module connected to the heater to control the heater, thereby keeping the temperature equalizing plate at a predetermined temperature; and a housing configured to accommodate the heat source module and the temperature control module, the housing having an opening, wherein the opening is configured to expose the temperature equalizing plate.

Abstract: A semiconductor device includes a substrate, at least one heterojunction bipolar transistor including a semiconductor unit and an electrode unit, an insulation unit, and a heat dissipation unit. The insulation unit covers the substrate and the heterojunction bipolar transistor such that a collector electrode, a base electrode and an emitter electrode of the electrode unit are electrically isolated from one another. The insulation unit is formed with an opening to expose an electrode wire of the emitter electrode. The heat dissipation unit covers the electrode wire and is made of an electrically conductive and heat dissipating material, and has a thickness that is not less than 3 ?m.

Abstract: The disclosure is directed to an ex vivo cell culture system and methods of using the cell culture system to identify potential therapeutic agents for the treatment of leukemia or lymphoma, such as chronic lymphocytic leukemia (CLL). The ex vivo culture system comprises (a) a first cell culture comprising bone marrow stromal cells (BMSC) which express one or more exogenous cell signaling molecules; (b) a second cell culture comprising leukemia or lymphoma cells isolated from a human; and optionally (c) one or more soluble cell signaling molecules.

Abstract: A pad structure includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located above the substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and between the conductive layer and the pad layer. The conductive layer includes a number of effective blocks, and a proportion of a block area of a block of the effective blocks to a total block area of the effective blocks ranges between 40%-50%. The block has at least one hollow portion, wherein the hollow portion has a total hollow area, and a ratio of the total hollow area to the block area ranged between 0.1 and 0.5.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.

Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.

Abstract: An online system receives an advertisement (“ad”) request identifying an application, one or more items for use within the application, ad content, and a prompt for purchasing one or more of the items. The prompt for purchasing an item comprises text or image data describing the purchasing and instructions that, when executed by a client device, request payment information from a user accessing the prompt. When the ad content is presented to a user, the prompt is also presented. When the user interacts with the prompt, payment information is requested and communicated to a third party system associated with the application. The ad content and prompt may be presented to the user within a feed of content items provided to the user by the online system.

Abstract: A buoyancy dry bag includes an air valve unit, and first and second body parts that are connected to each other and that cooperatively define a receiving space. The first body part has a lining layer made of thermoplastic polyurethane, and an external layer structure having an inner layer disposed at an outer side of the lining layer and made of thermoplastic polyurethane, an outer layer contacting an outer surface of the inner layer and made of polyester, and a pattern layer contacting the outer layer. The first body part defines a first air chamber between the lining layer and the inner layer. The air valve unit includes a first air valve mounted to the external layer structure for injection of air into the first air chamber therethrough.

Abstract: Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.

Abstract: Complex concentrated alloys include five or more elements, at least one of which is ruthenium. Example complex concentrated alloys can include nickel and chromium, iron, ruthenium, molybdenum, and/or tungsten. Example complex concentrated alloys have single phase microstructure of face centered cubic (FCC) and can be homogenous. Example complex concentrated alloys can exhibit improved corrosion resistance.

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.