Patents by Inventor Pin Lu

Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190000202
    Abstract: A buoyancy dry bag includes an air valve unit, and first and second body parts that are connected to each other and that cooperatively define a receiving space. The first body part has a lining layer made of thermoplastic polyurethane, and an external layer structure having an inner layer disposed at an outer side of the lining layer and made of thermoplastic polyurethane, an outer layer contacting an outer surface of the inner layer and made of polyester, and a pattern layer contacting the outer layer. The first body part defines a first air chamber between the lining layer and the inner layer. The air valve unit includes a first air valve mounted to the external layer structure for injection of air into the first air chamber therethrough.
    Type: Application
    Filed: May 18, 2018
    Publication date: January 3, 2019
    Inventor: Kuo-Pin LU
  • Publication number: 20180374763
    Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 27, 2018
    Inventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
  • Patent number: 10153203
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin
  • Publication number: 20180276337
    Abstract: The present invention provides a method for identifying radiation induced genes and long non-coding RNAs and its application thereof, the method comprises the steps of: (1). Provide expression values of genes and long non-coding RNAs; (2). Execute weighted gene correlation network analysis (WGCNA) by a computer system to calculate Pearson correlation coefficients of pairs of the genes and long non-coding RNAs based on the expression values of the genes and long non-coding RNAs; and (3). Perform a screening step by the computer system to identify radiation induced genes and long non-coding RNAs based on the Pearson correlation coefficients of the pairs of the genes and long non-coding RNAs with a value more than 0.75.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Eric Y. Chuang, Tzu-Pin Lu, Mong-Hsun Tsai, Liang-Chuan Lai, Wei-An Wang
  • Patent number: 10056395
    Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 21, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chi-Pin Lu, Pei-Ci Jhang, Fu-Hsing Chou, Chih-Hsiung Lee
  • Patent number: 10049948
    Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 14, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
  • Publication number: 20180151429
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Application
    Filed: August 1, 2017
    Publication date: May 31, 2018
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin
  • Publication number: 20180144098
    Abstract: A drug combination prediction method comprising: storing a plurality of original gene sets, at least one first gene impacted by a first drug and at least one second gene impacted by a second drug; determining the part of the at least one first gene and the part of the at least one second gene to be a first interaction gene set; calculating a gene amount of the first interaction gene set to obtain a first interaction gene amount, and calculating a first percentage generated by the first interaction gene amount in the first original gene set; calculating an interaction value of the combination of the first drug and the second drug according to the first percentage; and selecting at least one synergistic pharmaceutical composition according to the interaction value.
    Type: Application
    Filed: December 1, 2016
    Publication date: May 24, 2018
    Inventors: Wei-I LIU, Yu-Shian CHIU, Joey Jen-Hui SYU, Chia-Shan HSIEH, Mong-Hsun TSAI, Tzu-Pin LU, Liang-Chuan LAI, Eric Y. CHUANG, Hui-I HSIAO
  • Publication number: 20180073081
    Abstract: The invention is directed to a method to predict prognostic results for diseases including acute myeloid leukemia (AML) by analyzing novel markers which comprises microRNA/mRNA (miRNA/mRNA) pairings. In particular, the miRNA/mRNA pairings are a kind of NPM1 mutation-modulated miRNA/mRNA regulation pairs.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: Eric Y. Chuang, Mong-Hsun Tsai, Wen-Chien Chou, Liang-Chuan Lai, Hwei-Fang Tien, Yu-Chiao Chiu, Tzu-Pin Lu, Yen-Chun Liu, Yi-Yi Kuo, Hsin-An Hou, Yidong Chen
  • Publication number: 20180019254
    Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.
    Type: Application
    Filed: October 14, 2016
    Publication date: January 18, 2018
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Pei-Ci Jhang, Chi-Pin Lu, Jung-Yu Shieh
  • Publication number: 20170287921
    Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.
    Type: Application
    Filed: October 11, 2016
    Publication date: October 5, 2017
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHI-PIN LU, PEI-CI JHANG, FU-HSING CHOU, CHIH-HSIUNG LEE
  • Publication number: 20170147744
    Abstract: A system for analyzing sequencing data of bacterial strains and a method thereof are provided. The method for analyzing sequencing data of bacterial strains includes the following steps: searching a specific variable region of a first genetic sample sequence and searching another specific variable region of a second genetic sample sequence; determining whether both the specific variable region and the another specific variable region have an identical cross-sample subsequence; if both the specific variable region and the another specific variable region have the identical cross-sample subsequence, storing the cross-sample subsequence into a recording table; and if the identical cross-sample subsequence exists, comparing the cross-sample subsequence with a plurality of gene sequences of known strains stored in a database module to analyze a plurality of strains corresponding to the cross-sample subsequence in the first genetic sample sequence and the second genetic sample sequence.
    Type: Application
    Filed: December 8, 2015
    Publication date: May 25, 2017
    Inventors: Chia-Yang CHENG, Joey Jen-Hui, SYU, Wei-I LIU, Mong-Hsun TSAI, Tzu-Pin LU, Liang-Chuan LAI, Eric-Y CHUANG
  • Publication number: 20170098478
    Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20170077118
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: CHENG-HSIEN CHENG, CHIH-WEI LEE, SHAW-HUNG KU, WEN-PIN LU
  • Patent number: 9589982
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 7, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 9524784
    Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20160336339
    Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.
    Type: Application
    Filed: October 13, 2015
    Publication date: November 17, 2016
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 9437612
    Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 9383990
    Abstract: A server includes a detecting module, a calculating module, a comparing module, an allocating module and a sorting module. The detecting module is used for receiving firmware version query information from a plurality of client devices. The calculating module is used for calculating bandwidth sum of the CPEs. The comparing module is used for determining whether the calculated total bandwidth is larger than a total downloading bandwidth of the server. The allocating module is used for sequencing the client devices which transmit the firmware download requests to wait for the download. The sorting module is used for scoring each of the client devices which transmit the firmware download requests according to attributes of the client devices which transmit the firmware download requests and sequencing the client devices which transmit the firmware download requests to wait for downloading according to the scores.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: July 5, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Pin Lu, Ming-Chen Tsai
  • Publication number: 20160180398
    Abstract: An online system receives an advertisement (“ad”) request identifying an application, one or more items for use within the application, ad content, and a prompt for purchasing one or more of the items. The prompt for purchasing an item comprises text or image data describing the purchasing and instructions that, when executed by a client device, request payment information from a user accessing the prompt. When the ad content is presented to a user, the prompt is also presented. When the user interacts with the prompt, payment information is requested and communicated to a third party system associated with the application. The ad content and prompt may be presented to the user within a feed of content items provided to the user by the online system.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Pin Lu, Derek Chirk Yin Cheng