Patents by Inventor Ping Chen

Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220397873
    Abstract: A transaction harmony degree-based method and system for transaction matching between a power grid and building energy. The method includes: obtaining a transaction harmony degree of a historical transaction cycle; sending, by using a blockchain, the transaction harmony degree to a corresponding building energy user, and sending a maximum compensated electricity price and an expected compensated electricity price in peak-valley regulation to all building energy users; determining, by each building energy user, a transaction-based compensated electricity price in the peak-valley regulation based on the received transaction harmony degree and the received maximum compensated electricity price and expected compensated electricity price in the peak-valley regulation, and feeding back the transaction-based compensated electricity price in the peak-valley regulation to a power grid; and determining, by the power grid, a building energy user that successfully performs transaction matching with the power grid.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 15, 2022
    Inventors: Shuang Zeng, Xianglong Li, Yifeng Ding, Anqi Liang, Mingquan Qiu, Zhao Wang, Ping Chen, Qijing Xing, Lin Ma, Dapeng Duan, Huanna Niu, Xuwu Ge, Zongsheng Li
  • Patent number: 11525814
    Abstract: A method for identifying converters from tobacco seedling population. The method includes: 1) sowing and cultivating tobacco seeds to be identified for 45-55 days; sampling a plurality of leaf disks from each of 45-55 days old seedlings; 2) incubating the plurality of leaf disks of each seedling in a sealed container at 37° C. for 10-12 hours, thereby obtaining a plurality of incubated tobacco leaves of each seedling; 3) immersing the plurality of incubated tobacco leaves of each seedling in an extractant, extracting alkaloids and obtaining an extract of each seedling; 4) analyzing the amounts of nicotine and nornicotine in the alkaloids extract of each seedling; and 5) automatically recognizing peaks of the alkaloids extract of each seedling, and calculating the percent nicotine conversion (PNC) and the pseudo percent nicotine conversion (PPNC).
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 13, 2022
    Assignee: YUNNAN ACADEMY OF TOBACCO AGRICULTURAL SCIENCES
    Inventors: Yong Li, Tao Pang, Xuejun Chen, Xueyi Sui, Junli Shi, Yongping Li, Guanghui Kong, Ping Chen, Yuping Wu
  • Publication number: 20220392551
    Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 8, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
  • Publication number: 20220393323
    Abstract: A manufacturing method of a lithium battery cell is provided and has steps of providing an bag, electrode sheets and a conduit, a part of an edge of the bag being pressed to form an sealing edge, an electrode chamber being enclosed in the bag, the electrode sheet being accommodated in the electrode chamber, the sealing edge being strip-shaped and an air chamber being formed therein, the air chamber being communicated to the electrode chamber, the conduit being disposed on the sealing edge, two ends of the conduit being an inner end and an outer end, the inner end being communicated to the air chamber and separated from the electrode chamber, and the outer end being exposed from the bag; injecting an electrolyte into the electrode chamber through the conduit; pressing the air chamber to form a secondary sealing edge; cutting the secondary sealing edge to remove the conduit.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Inventors: Chueh-Yu KO, Chiang-Ping CHEN
  • Publication number: 20220393976
    Abstract: Example methods and computer systems for packet handling for active-active stateful service insertion are disclosed. One example may involve a computer system detecting a packet addressed from a source address to a service endpoint address. Based on configuration information associated with the service endpoint address, the computer system may identify a first active logical service router (SR) and a second active logical SR that are both associated with the service endpoint address and configured to operate in an active-active mode. The first active logical SR may be selected over the second active logical SR by mapping tuple information to the first active logical SR. The computer system may generate an encapsulated packet by encapsulating the packet with an outer header addressed to an outer destination address associated with the first active logical SR and send the encapsulated packet towards the first active logical SR for processing according to a stateful service.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 8, 2022
    Applicant: VMware, Inc.
    Inventors: Bo LIN, Dong Ping CHEN, Wei WANG, Yi ZENG, Xinyu HE, Dahui YUAN, Xiao LIANG
  • Patent number: 11521691
    Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Hua-Ling Hsu, Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang
  • Patent number: 11522073
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee
  • Publication number: 20220384974
    Abstract: A tubular high current female terminal for mating with a male terminal having an outer terminal, and at least one core terminal. The outer terminal includes at least a mating portion and a termination portion. The core terminal includes a plurality of spring contacts, and preferably, latches for attaching thereof on an elongated opening of the outer terminal. The outer terminal is a seamless preformed tube that extends from the mating portion integrally extending to the termination portion as a single piece. A plurality of tubular high current female terminals may be joined together at termination portions thereof. Also, the tubular high current female terminal may have mating portions at opposing ends thereof, such that the male terminals respectively connected thereto extend at any desired angle. Furthermore, the mating portion may be a cylindric tube for mating with a cylindric male terminal, while the termination portion is attachable to an electrical cable.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: J.S.T. CORPORATION
    Inventor: Ping CHEN
  • Publication number: 20220384617
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220384263
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Patent number: 11516125
    Abstract: Example methods and computer systems for packet handling for active-active stateful service insertion are disclosed. One example may involve a computer system detecting a packet addressed from a source address to a service endpoint address. Based on configuration information associated with the service endpoint address, the computer system may identify a first active logical service router (SR) and a second active logical SR that are both associated with the service endpoint address and configured to operate in an active-active mode. The first active logical SR may be selected over the second active logical SR by mapping tuple information to the first active logical SR. The computer system may generate an encapsulated packet by encapsulating the packet with an outer header addressed to an outer destination address associated with the first active logical SR and send the encapsulated packet towards the first active logical SR for processing according to a stateful service.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 29, 2022
    Assignee: VMWARE, INC.
    Inventors: Bo Lin, Dong Ping Chen, Wei Wang, Yi Zeng, Xinyu He, Dahui Yuan, Xiao LiANG
  • Patent number: 11515316
    Abstract: A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 29, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tzu-Ping Chen
  • Publication number: 20220377359
    Abstract: One or more computing devices, systems, and/or methods for video encoding are provided. For example, a video file may be segmented into at least a first portion and a second portion. The first portion may be analyzed to determine that the first portion is associated with a first level of complexity, and the second portion may be analyzed to determine that the second portion is associated with a second level of complexity. A first bitrate associated with the first level of complexity may be determined, and a second bitrate associated with the second level of complexity may be determined. The first portion may be encoded at the first bitrate to generate a first encoded portion, and the second portion may be encoded at the second bitrate to generate a second encoded portion. The first encoded portion and the second encoded portion may be assembled to generate an optimized video file.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 24, 2022
    Inventors: Jian Zhou, Congxia Dai, Heri Zhao, Zhonghua Ma, Xumin Wu, Michael Chang-Ping Chen, Sagar Dattatraya Bhandare
  • Publication number: 20220374560
    Abstract: The invention discloses a mechanics calculation method of drill bit tooth considering rock dynamic strength and mixed crushing mode, including: Step S1: selecting a target drill bit tooth and a target rock, and determining a type of target drill bit tooth, a geometry of the target drill bit tooth, a rock type and rock parameters of the target rock; Step S2: calculating a horizontal cutting force of the target drill bit tooth according to a horizontal cutting mechanics calculation method of drill bit tooth; Step S3: calculating a vertical penetration force of the target drill bit tooth according to a vertical penetration mechanics calculation method of drill bit tooth; Step S4: calculating a resultant force experienced by the target drill bit tooth according to a resultant force calculation method of drill bit tooth. The invention provides a calculation method for accurately obtaining drill bit tooth mechanics under different working conditions.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 24, 2022
    Applicant: SOUTHWEST PETROLEUM UNIVERSITY
    Inventors: Guangjian Dong, Ping Chen, Jianhong Fu, Yingxin Yang
  • Publication number: 20220361579
    Abstract: A porous liquid conducting member with a smooth liquid conduction is provided, the liquid conducting member is of a porous material and provided with a hollow cavity therein, and includes an inner side and an outer side. The inner side or the outer side is configured to be in contact with a liquid, and is provided with an air exchange recess to form a thin-wall on the liquid conducting member. A wall thickness of the thin-wall is smaller than a wall thickness between the inner side and the outer side, enabling air to be conducted through the thin-wall. The air exchange recess is outside a heating area of the liquid conducting member, so that air can enter the liquid storage chamber through the air exchange recess during an atomizing process, to avoid porous channels in the heating area from being occupied by the air entering the liquid storage chamber.
    Type: Application
    Filed: September 28, 2020
    Publication date: November 17, 2022
    Inventor: Ping Chen
  • Publication number: 20220366652
    Abstract: The disclosure provides a display image adjustment method and an augmented reality display device. The display image adjustment method includes the following steps. Received image data is converted to a coordinate system of the augmented reality display device to obtain initial coordinate information. An initial image is provided to an active display region of the augmented reality display device based on the initial coordinate information. The initial coordinate information is adjusted in a virtual adjustment coordinate region to obtain adjusted coordinate information when an adjustment command is received. An adjusted image is provided to the active display region of the augmented reality display device based on the adjusted coordinate information. The display image adjustment method and the augmented reality display device proposed by the disclosure may adjust display content of the AR display device according to user's needs.
    Type: Application
    Filed: April 14, 2022
    Publication date: November 17, 2022
    Applicant: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Publication number: 20220367672
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao LIN, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20220368275
    Abstract: Provided is a multifunctional base, which includes a first cover, having a first connecting edge made of flexible material and extended along a periphery of the first cover, the first connecting edge is configured to sealingly connect the multifunctional base with an object; and a second cover, the second cover is connected with first cover to define a receiving space. A bag is also provided.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventor: Song Ping Chen
  • Patent number: 11502795
    Abstract: A multi-user downlink orthogonal frequency-division multiple access (OFDMA) configuration method includes: assigning contiguous resource units (RUs) included in a channel to a plurality of stations, respectively; and assigning, by an access point (AP), one modulation and coding scheme (MCS) to each of the plurality of stations. Data rates of modulation and coding schemes that are assigned to first stations and associated with contiguous first RUs assigned to the first stations are monotonic, where the first stations are included in the plurality of stations.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: November 15, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Ying-You Lin, Kuan-I Li, Ping-Chen Lin, Po-Hsun Wei, Cheng-Yi Chang
  • Publication number: 20220359266
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Hsiu-Wen Hsueh, Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu