Abstract: A method for preparing a modular planar interconnect plate includes steps of a) providing a metal blank sheet having a main region and two first lateral regions, b) forming two openings respectively in the first lateral regions, and c) stamping to form protrusions and depressions at the main region on lower and upper surfaces of the metal blank sheet. In the stamping step, each of two lower surrounding protrusions and two upper surrounding depressions is formed to surround a corresponding one of the openings, and each of an upper surrounding protrusion and a lower surrounding depression is formed to surround the first lateral regions and the corresponding ones of the protrusions and depressions formed at the main region.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A portable power pack having a housing, a rechargeable lithium battery positioned in the housing, a liquid crystal display (LCD), a wireless charging coil, a light emitting diode (LED) flash light, a universal serial bus (USB) port, a direct current (DC) port, and a power management circuit. The LCD can be positioned on the housing and configured to display a status of the portable power pack. The wireless charging coil can be positioned in or on the housing and configured to wirelessly couple with an external wireless charging coil of an external device through electromagnetic induction in accordance with, for example, the Qi wireless power transfer standard. The USB port supplies a charging current to charge a portable electronic device, while the DC port supplies a starting current to jump start an engine of a vehicle that is electrically coupled with an external battery.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: An integrated circuit includes a diode for generating a temperature dependent voltage, a resistor divider for generating divided voltages by dividing the temperature dependent voltage, and a multiplexer circuit for selecting one of the divided voltages as a reference voltage used for setting a supply voltage.

Abstract: Disclosed herein are compounds of formula (I) which are inhibitors of an IDO enzyme: (I). Also disclosed herein are uses of the compounds in the potential treatment or prevention of an IDO-associated disease or disorder. Also disclosed herein are compositions comprising these compounds. Further disclosed herein are uses of the compositions in the potential treatment or prevention of an IDO-associated disease or disorder.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A polishing pad is provided. The polishing pad comprises a polishing layer and a metal-containing layer. The polishing layer has a polishing surface and a backside surface opposite to each other, wherein the backside surface has a plurality of cavities. The metal-containing layer is disposed on the backside surface of the polishing layer and fills into the cavities, wherein a first contact area is between the metal-containing layer and the backside surface of the polishing layer, and the first contact area is larger than the orthogonal projection area of the polishing layer.

Abstract: An efficient reinforced heating assembly, including a reinforcing frame, a liquid conducting member and at least two heating members. The reinforcing frame is provided with a vent opening for air to pass therethrough. The at least two heating members are disposed on the reinforcing frame, disposed in the vent opening or covered on the vent opening, to be in contact with the air. The liquid conducting member is disposed on a side of the heating member and in contact with the heating member, so that the liquid conducting member is able to conduct an external liquid to the heating member for heating and atomizing to generate an aerosol, which is output via the vent opening. An atomizing device is further provided, including a shell and the efficient reinforced heating assembly disposed in the shell. The reinforcing frame supports the heating member to improve the strength of the heating member.

Abstract: An adhesive structure is provided, which includes a plastic substrate, and an adhesive layer on the plastic substrate. The adhesive layer includes a releasable adhesive. The adhesive layer has a Young's modulus of 5 MPa to 14 MPa and an adhesive force to glass of 200 gf/25 mm to 2000 gf/25 mm. The adhesive structure can be used to transfer a device.

Abstract: An optical fingerprint sensor (OFPS) for use with a liquid-crystal display (LCD) panel having a backlight module is positioned under the backlight module and captures an image of a fingerprint sensing area on the LCD panel through an aperture in both a reflector and a metal shield of the backlight module. The OFPS includes a sensor layer, a wafer-level optic layer bonded to the sensor layer and an infrared pass filter (IRPF) coating formed on a substantially flat top surface of the wafer-level optic layer. An OFPS may be formed with a flat top and may include a wafer-level optic layer having one or more lenses to direct light generated by a light source beneath the wafer-level optic layer. The wafer-level lenses may be bonded with the fingerprint scanner. The flat top of the OFPS may be made with an IRPF coating.

Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

Abstract: Generating, by a first primary site that is included in a group of primary sites of a distributed database system, a commit action redo log message for a commit action performed by the first primary site for a first database transaction, the commit action redo log message including a transaction ID for the first database transaction and a transaction order indicator that represents an order of database transactions in a group of database transactions performed at one or more primary sites of the group of primary sites; and sending, by the first primary site, the commit action redo log message, for a corresponding first standby site that backs up the first primary site.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Abstract: An electrical female terminal for mating with a connector assembly generally including a main body, a two-bodied spring, A protrusion extends from an unattached end portion of the lever member, the protrusion having faces angled relative to each other to efficiently deflect the lever member upwards when the protrusion interacts with an internal protrusion of a housing or a connector assembly, which in turn makes the electrical female terminal more difficult to remove from the housing or the connector assembly to thereby protect the electrical female terminal against the electrical female terminal from falling out during use. A top portion of the retainer member of the electrical female terminal, located above the two-bodied spring, has a dimple portion to increase the number of contacts to an upper spring of the two-bodied spring, so as to increase the stiffness of the two-bodied spring.

Abstract: An electrical female terminal for mating with a connector assembly generally including a main body, a two-bodied spring, and a wire fastening portion. A protrusion extends from an unattached end portion of the lever member, the protrusion having faces angled relative to each other to efficiently deflect the lever member upwards when the protrusion interacts with an internal protrusion of a housing or a connector assembly. A top portion of the retainer member of the electrical female terminal, located above the two-bodied spring, has a dimple portion. The terminal face or leading end portion of the electrical female terminal is prevented from damaging or cutting a silicone seal. The overstress feature of the tang member of the lever is improved upon by relocating and reshaping the protruding member thereof. The configuration or shape of the cross-section across the upper portion and the support member at the front end portion of the main body of the electrical female terminal is substantially U-shaped.