Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.

Abstract: A trench gate metal oxide semiconductor (MOSFET) device includes a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.

Abstract: MRI system cabinet having a cabinet body with electronics and a water cooler with a water cooling loop. The water cooling loop divides the cabinet body into first and second cabinet spaces, and the electronics are along the first and second cabinet spaces. An air cooler is along the central axis of the water cooler and has a fan. A cooling cycle is formed where, on a first side, the fan generates a first air flow, which is sent to the first cabinet space through a first air path, and a second air flow, which is sent to the second cabinet space through a second air path. After flowing through the first and second cabinet spaces, the first and second air flows are guided into the water cooling loop for heat exchange under the suction action of the fan on a second side, and then directed into the air cooler.

Abstract: A keyboard includes a substrate, a display member, and a keyswitch assembly. The display member is disposed over the substrate. The keyswitch assembly includes a keycap, a fixing element, two balance bars, and a position-returning member. The keycap is located over the substrate and has a light-transmitting portion located over the display member. The fixing element is disposed on the substrate and has a retaining slot. Each of the balance bars includes a rod portion and an end portion. The rod portion is rotatably engaged with the keycap. The end portion is movably retained in the retaining slot. The position-returning member abuts against the keycap above the substrate and is adjacent to an edge of the keycap.

Abstract: A video processing method for detecting location(s), pixels, and skeleton(s) of one or more objects and an associated video processing circuit are provided. The video processing method may include: utilizing a backbone network in a predetermined model of a single deep learning network to receive and convert input image data having the object(s) into at least one feature map; and utilizing at least one instance head and a pixel head in the predetermined model of the single deep learning network to receive and convert the aforementioned at least one feature map into one or more object detection results, one or more instance segmentation results and one or more pose estimation results of the object(s).

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: A display device is provided. The display device includes a device housing, a knob, a restriction unit and a screen panel. The knob is rotatably connected to the device housing, wherein the knob comprises a latch and a plurality of teeth, the knob is adapted to be rotated between a first knob location and a second knob location, and when the knob is in the first knob location, the latch protrudes from the device housing, and when the knob is in the second knob location, the latch is received in the device housing. The restriction unit is disposed in the device housing, wherein the restriction unit is adapted to be connected to one of the teeth to restrict the knob. The screen panel is detachably connected to the device housing. The display device can be easily detached from a display system.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.

Abstract: A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling an conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: A method includes forming a first conductive feature over a substrate, forming an etch-stop layer (ESL) stack over the first conductive feature, forming a first interlayer dielectric (ILD) layer over the ESL stack, forming a patterned ESL having a first opening over the first ILD layer, forming a second ILD layer over the patterned ESL, thereby filling the first opening, forming a patterned HM having a second opening over the second ILD layer, where a width of the second opening is greater than a width of the first opening, performing an etching process to form a first trench in the second ILD layer and a second trench in the first ILD layer, where the second trench exposes the first conductive feature, and subsequently depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature interconnecting a third conductive to the first conductive feature.

Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.

Abstract: An Insulation Displacement Contact Compliant connector system (IDCC) which includes a housing, header pins, and a Printed Circuit Board (PCB). Each header pin has at least a single barb to be retained into the housing. Each pin has a blade for contacting a wire. A compliant feature on the pin retains itself into holes in the PCB. The housing has a negative space similarly shaped to the pin. The housing includes a strain relief which provides a lead-in for a wire. When the system is fully assembled, the pins reside in the housing, and exit through the housing and into and through respective holes in the PCB. A wire can be inserted into the housing once the pins reside in the housing. There are several options for the assembly process including a) a pin-to-housing insertion process; b) a housing assembly-to-PCB process or a connector-to-PCB process; and c) a wired housing assembly-to-PCB assembly process or a wire harness-to-PCB assembly process.

Abstract: The invention provides a frame-type heating assembly, including a heating sheet and a reinforcing frame. The heating sheet includes a heating portion and a connecting portion that is connected to the heating portion and configured for electrical connection with an external circuit. The heating sheet and the reinforcing frame are arranged side by side to improve the strength of the heating sheet. The invention further provides a heating unit including the heating assembly, a liquid conducting member configured for conducting liquid to the heating assembly, and a cover. The invention further provides an atomization system including a housing and the heating assembly disposed in the housing. The side of the heating assembly where the heating sheet is located faces an inner wall of the housing. The reinforcing frame body plays a role in supporting the heating sheet, so that the strength of the heating sheet is improved.

Abstract: A light-curing resin composition, a three-dimensional object containing the same, and a manufacturing method of the three-dimensional object are provided. The light-curing resin composition includes a photoinitiator, an acrylic oligomer, an acrylic monomer, and expandable particles with hollow spherical shell structures. The acrylic monomer is a monofunctional monomer, a difunctional monomer, or a combination thereof.

Abstract: A variety of methods, systems, and compositions are disclosed, including, in one embodiment, method of scale inhibition including: introducing a treatment fluid comprising a brine, a scale inhibitor in neutralized form, and a thermally activated acid precursor through a wellbore and into a producing formation; wherein the thermally activated acid precursor is heated to release an acid that enhances miscibility of the scale inhibitor in the brine.