Abstract: A lipid composition includes, by weight of the lipid composition: from 30 wt % to 70 wt % a first lipid component; from 10 wt % to 40 wt % a sweetening substance; from 5 wt % to 20 wt % water; from 0.1 wt % to 1.2 wt % an emulsifier; and 1.5 wt % to 11 wt % a second lipid component. The emulsifier has a SFA content of less than 90 wt %. The second lipid component has a SFA content of at least 90 wt %, and fully saturated fatty acids with a carbon chain of more than 16 carbons comprise C22:0 and account for at least 33.3 wt % of the SFA content of the second lipid component by weight. The lipid composition has a SFA content of at least 40 wt %, and fully saturated fatty acids with a carbon chain of more than 16 carbons account for at least 12.5 wt % of the SFA content of the lipid composition by weight.

Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

Abstract: One or more computing devices, systems, and/or methods for video encoding are provided. For example, a video file may be segmented into at least a first portion and a second portion. The first portion may be analyzed to determine that the first portion is associated with a first level of complexity, and the second portion may be analyzed to determine that the second portion is associated with a second level of complexity. A first bitrate associated with the first level of complexity may be determined, and a second bitrate associated with the second level of complexity may be determined. The first portion may be encoded at the first bitrate to generate a first encoded portion, and the second portion may be encoded at the second bitrate to generate a second encoded portion. The first encoded portion and the second encoded portion may be assembled to generate an optimized video file.

Abstract: In some embodiments, the present disclosure relates to a chemical mechanical planarization (CMP) tool. The CMP tool includes a carrier and a malleable membrane coupled to the carrier and having a lower surface facing away from the carrier. The lower surface of the malleable membrane includes a first malleable material within a central region of the lower surface and a second malleable material within a peripheral region of the lower surface, which surrounds the central region. The first malleable material provides the central region of the lower surface with a first stiffness and the second malleable material provides the peripheral region of the lower surface with a second stiffness that is different than the first stiffness.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: The disclosure comprises a stylus and a touch control system. The stylus comprises a pen body, a pen tip, and a light emitting device. The light emitting device is provided at the pen tip. A non-contacting end of the pen tip is connected to a bottom end of the pen body. The pen body is provided with a control module inside the pen body. The control module is electrically connected to the light emitting device and controls the light emitting device to emit light when a contacting end of the pen tip is applied to a reflective display.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

Abstract: A circuit for reverse battery protection includes an isolation circuit and a control circuit. The isolation is circuit coupled between a gate output of an electronic fuse (E-fuse) and at least one external metal-oxide-semiconductor field-effect transistor (MOSFET). The E-fuse is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller. The isolation circuit is configured to disconnect the gate output from the at least one external MOSFET when the battery is installed with reverse polarity. The control circuit is coupled between the external ground pin and the at least one external MOSFET. The control circuit is configured to turn on the at least one external MOSFET when the battery is installed with the reverse polarity.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

Abstract: A hydrogenolysis/hydrogenation catalyst includes copper oxide, calcium oxide, silicon dioxide, and sodium oxide, wherein the hydrogenolysis/hydrogenation catalyst is a powder, tablet, or extrudate, the hydrogenolysis/hydrogenation catalyst is substantially free of chromium, the hydrogenolysis/hydrogenation catalyst exhibits a crystallite phase of CuO and an additional crystallite phase selected from the group consisting of cubic SiO2, rhombohedral calcium carbonate CaCO3, anorthic calcium silicate CaCO3, calcium silicate hydroxide hydrate (Ca14Si24O58(OH)8·5H2O), calcium silicate hydrate 4CaO·5 SiO2·5H2O, alumina, and combinations of two or more thereof.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: A method for replacing an identity certificate in a blockchain network includes a service subnet, a consensus subnet, and a routing layer used for isolating the service subnet from the consensus subnet. The method includes: receiving a root certificate replacement notification transmitted by a certificate authentication center; obtaining a public key corresponding to the certificate authentication center; verifying the root certificate replacement notification by using the obtained public key; forwarding the root certificate replacement notification to a consensus node in the consensus subnet after the validation succeeds, so that the consensus node records the root certificate replacement notification into a latest data block after a consensus on the root certificate replacement notification is reached; and requesting, when the data block is received, the certificate authentication center to replace an identity certificate.

Abstract: Compounds with KRAS G12C inhibitory active are disclosed and methods of using the same to treat a cancer comprising a K-Ras G12C mutation.

Abstract: An electrical connector having a housing for receiving therein at least one terminal; a hinged cover, operably coupled to the housing, for covering the terminal received by the housing; at least a hinge member operably coupled to the housing and the hinged cover; and an independent secondary terminal lock (ISL) within the hinged cover for locking the terminal within the housing when the hinged cover is at a closed position. The ISL blocks the terminal from being removed or dislodged from the housing. The housing and the hinged cover have a locking mechanism that retains and secures the hinged cover onto the housing, and thereby locks the terminal within the housing. Alternatively, the housing and the hinged cover have another locking mechanism that includes a substantially flexible member having an elongated slot and extending from a side portion of the housing for accommodating therein at least an elongated retention member extending from at least a side of the hinged cover.

Abstract: Disclosed is a method for preparing high-strength coral aggregate concrete under low pressure conditions, including the following steps: weighing cement, mineral admixture, coral aggregate, mixing water, water reducer, and defoamer; mixing the cement and the mineral admixture well to obtain a cementing material; putting the coral aggregate, sea water, water reducer, defoamer, and 55-85% of the cementing material into a closed mixing system to stir for 10-15 min under low pressure conditions, and pouring the remaining cementing material into the mixing system to stir for additional 10-15 min to prepare the high-strength coral aggregate concrete. The high-strength coral aggregate concrete obtained has advantages of high mechanical properties, high compactness, excellent impermeability and durability, drawing on local resources in construction engineering on remote islands and reefs, and maximum resource utilization.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: An electrical male terminal of this invention includes a clamp or crimp area, a main body, and a blade. Protruding members and support members of the main body act as overstress protection. A panel shield member protects a protruding guide member. In another embodiment of this invention, a protruding member extends from a first support member of the main body, and a cut-out portion at the lower portion of the main body accommodates therein the protruding member. Furthermore, in this another embodiment of the electrical male terminal of this invention, a protrusion extends from the unattached end portion of the lever member to protect the electrical male terminal from inadvertently falling out during use. The configuration or shape of the cross-section across the upper portion at the front portion of the main body and the support member at the front portion of the main body of the electrical male terminal is substantially U-shaped.

Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.