Abstract: A hallux valgus traction device is disclosed. The hallux valgus traction device includes a first traction unit, a second traction unit and a connection unit. The first traction unit and the second traction unit wind around a first metatarsal bone and a second metatarsal bone respectively. The first traction unit and the second traction unit are connected to each other through the connection unit. When the connection unit is tightened, the connection unit brings the first traction unit and the second traction unit to approach each other, so that the first metatarsal bone and the second metatarsal bone also approach each other.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: A data unit processing method performed by a first communication device, comprising: configuring a data unit by the first communication device, the data unit comprising: a specific format preamble following a first packet format; and a symbol part, comprising at least one symbol and following a Wi-Fi long range packet format. The specific format preamble can be decoded according to a first communication standard and the symbol can be decoded according to a Wi-Fi long range mode. The symbol part can be identified according to the specific format preamble. A method can decode the above-mentioned data unit and a communication device can perform the methods are also disclosed.

Abstract: A developing method is provided. The developing method includes rotating a wafer. The developing method also includes dispensing, through a first nozzle, a developer solution onto the rotated wafer through a first nozzle at a first rotating speed. The developing method further includes dispensing, through a second nozzle, a rinse solution onto the rotated wafer through a second nozzle at a second rotating speed. The second rotating speed is less than the first rotating speed. In addition, the developing method includes simultaneously moving the first nozzle and the second nozzle during either the dispensing of the developer solution or the dispensing of the rinse solution.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: A developing method comprises steps as follows. A wafer is rotated. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved back and forth between a first position and a second position, in which moving the first nozzle back and forth is performed such that the first nozzle moving forward to the second position is reversed at the second position and that the first nozzle moving forward to the first position is reversed at the first position, and the first position and the second position are directly over the wafer, and the developer solution is dispensed through the first nozzle when moving the first nozzle back and forth between the first position and the second position.

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: An image sensor including a plurality of pixels and a plurality of pixel sensing circuits is provided. The pixels are arranged in a pixel array. The pixels are configured to sense an image to obtain a plurality of reference pictures. The pixels include a plurality of pixel types. The pixel sensing circuits are respectively and electrically connected to the pixels. The pixel sensing circuits are configured to respectively receive a photo current generated by each of the pixels. The pixels have different characteristic curves based on the pixel types, and at least one of an electrode structure parameter and an electrode bias of each of the pixels is determined according to a correspondingly characteristic curve. In addition, an image sensing method is also provided.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack.

Abstract: An image sensor and a manufacturing method thereof are provided. The image sensor includes a pixel sensing circuit, a pixel electrode, and an opto-electrical conversion layer. The pixel sensing circuit is corresponding to a plurality of pixel regions. The pixel electrode is disposed on the pixel sensing circuit. The pixel electrode includes a first electrode and a second electrode and is electrically connected to the pixel sensing circuit. The first electrode and the second electrode are coplanar, and have different polarities. The opto-electrical conversion layer is disposed on the pixel sensing circuit. The opto-electrical conversion layer includes a plurality of opto-electrical conversion portions, each of the opto-electrical conversion portions is corresponding to each of the pixel regions, and the opto-electrical conversion portions are separated from each other by a pixel isolation trench.

Abstract: An image sensor and a manufacturing method thereof are provided. The image sensor includes a pixel sensing circuit, a pixel electrode, and an opto-electrical conversion layer. The pixel sensing circuit is corresponding to a plurality of pixel regions. The pixel electrode is disposed on the pixel sensing circuit. The pixel electrode includes a first electrode and a second electrode and is electrically connected to the pixel sensing circuit. The first electrode and the second electrode are coplanar, and have different polarities. The opto-electrical conversion layer is disposed on the pixel sensing circuit. The opto-electrical conversion layer includes a plurality of opto-electrical conversion portions, each of the opto-electrical conversion portions is corresponding to each of the pixel regions, and the opto-electrical conversion portions are separated from each other by a pixel isolation trench.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Abstract: A data unit processing method performed by a first communication device, comprising: configuring a data unit by the first communication device, the data unit comprising: a specific format preamble following a first packet format; and a symbol part, comprising at least one symbol and following a Wi-Fi long range packet format. The specific format preamble can be decoded according to a first communication standard and the symbol can be decoded according to a Wi-Fi long range mode. The symbol part can be identified according to the specific format preamble. A method can decode the above-mentioned data unit and a communication device can perform the methods are also disclosed.

Abstract: A catheter apparatus includes a replaceable module, a main body portion and a sensing module. The main body portion includes a tube, a urine guide opening and an elastic unit. The replaceable module includes a control unit. A first terminal of the tube is coupled to the replaceable module and a second terminal of the tube is inserted into the bladder. The urine guide opening is disposed at the second terminal of the tube and used to guide urine into the tube when the second terminal of the tube is inserted into the bladder. The elastic unit is disposed at the second terminal of the tube and coupled to the control unit. The sensing module is coupled to the control unit and used to sense whether the second terminal of the tube is inserted to the correct position in the bladder and transmit sensing result to the control unit.

Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate. The method includes forming a protective layer over the surface of the semiconductor substrate in a first chamber after the first process. The method includes performing a first transferring process to transfer the semiconductor substrate from the first chamber into a substrate carrier. The method includes performing a second transferring process to transfer the semiconductor substrate from the substrate carrier into a second chamber. The semiconductor substrate is located in the substrate carrier during a substantially entire first time interval between the first transferring process and the second transferring process. The method includes removing the substantially entire protective layer in the second chamber. The method includes performing a second process over the surface of the semiconductor substrate.

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Abstract: A developing method comprises steps as follows. A wafer is rotated. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved back and forth between a first position and a second position, in which moving the first nozzle back and forth is performed such that the first nozzle moving forward to the second position is reversed at the second position and that the first nozzle moving forward to the first position is reversed at the first position, and the first position and the second position are directly over the wafer, and the developer solution is dispensed through the first nozzle when moving the first nozzle back and forth between the first position and the second position.