Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142498
    Abstract: A voltage detection device includes: a reference voltage latch circuit, outputting one of a first set of reference voltages and a second sets of reference voltages lower than the first set of reference voltages, as a third set of reference voltages according to a selection signal, and being selectively to be reset or to continue outputting the one of the first and second sets of reference voltages as the third set of reference voltages according to a first detection signal; a first voltage detector, generating the first detection signal according to a fourth set of reference voltages lower than or equal to the first set of reference voltages and an input voltage; a second voltage detector, generating a second detection signal according to the third set of reference voltages and the input voltage; and a digital circuit, generating the selection signal according to the second detection signal.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 2, 2024
    Inventor: Wei-Ping WANG
  • Publication number: 20240139359
    Abstract: The present invention relates to a control technology of an electronic household trash container, in particular, a circuit control method of induction trash can with cold cathode ultraviolet lamp deodorization, which includes steps of setting a working cycle and a turn-off cycle of a ultraviolet sterilization and deodorization circuit, setting up an infrared pulse testing circuit to work for a predetermine number of times per second during the working cycle, wherein each working time of the infrared pulse testing circuit is 1 ms˜8 ms.
    Type: Application
    Filed: June 2, 2023
    Publication date: May 2, 2024
    Applicant: Fujian Nashida Electronic Incorporated Company
    Inventor: Shi Ping Wang
  • Patent number: 11974460
    Abstract: A display substrate includes a plurality of sub-pixels. The display substrate further includes: a base substrate; a plurality of temperature sensors disposed on a first side of the base substrate; and a light-shielding layer disposed on a peripheral side, a side proximate to the base substrate, and a side away from the base substrate, of a temperature sensor in the temperature sensors. The temperature sensor is configured to detect a temperature of at least one of the plurality of sub-pixels. The light-shielding layer is configured to shield light emitted to the temperature sensor.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 30, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yangbing Li, Haisheng Wang, Xiaoliang Ding, Yunke Qin, Fangyuan Zhao, Wenjuan Wang, Ping Zhang
  • Patent number: 11969915
    Abstract: The present application disclosures a double production line and a rapid prefabrication process of a segmental beam. The double production line including two production machine and a track system provided on the construction ground; the production machine includes a fixed end mold, two side molds, a bottom mold trolley, a middle internal mold trolley and two side internal mold trolley; two side molds are positioned on two sides of the fixed end mold respectively, the fixed end mold and two side molds together define a pouring position with an end opening, two openings of the pouring position are arranged facing each other; the track system includes a transverse track and a longitudinal track communicated with each other, two pouring positions are both positioned in the extension path of the transverse track, and the longitudinal track is positioned between two pouring positions.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignees: CHINA RAILWAY GUANGZHOU ENGINEERING GROUP CO., LTD., China Railway Guangzhou Engineering Group Real Estate Co., Ltd.
    Inventors: Xiao Zhou, Xiaofeng Deng, Yongguang Chen, Zhouyu Xie, Gaofei Wei, Jiawei Yang, Ping Zhang, Beibei Cheng, Wenqiang Zheng, Ying Wang, Yuan Xu
  • Publication number: 20240137431
    Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.
    Type: Application
    Filed: January 16, 2023
    Publication date: April 25, 2024
    Applicants: Chung Yuan Christian University, KGI Securities Co. Ltd.
    Inventors: Yu-Kuen Lai, Chao-Lin Wang, He-Ping Li, Cheng-Han Chuang, Kai-Po Chang
  • Patent number: 11968910
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Patent number: 11968911
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: April 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Patent number: 11965040
    Abstract: The present invention provides modulators of complement activity. Also provided are methods of utilizing such modulators as therapeutics.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: April 23, 2024
    Assignee: RA PHARMACEUTICALS, INC.
    Inventors: Michelle Denise Hoarty, Ketki Ashok Dhamnaskar, Daniel Elbaum, Kristopher Josephson, Kelley Cronin Larson, Zhong Ma, Nathan Ezekiel Nims, Alonso Ricardo, Kathleen Seyb, Guo-Qing Tang, Douglas A. Treco, Zhaolin Wang, Ping Ye, Hong Zheng, Sarah Jacqueline Perlmutter, Robert Paul Hammer
  • Patent number: 11968249
    Abstract: A coordinator module for improving communications within a cloud computing system is disclosed. The coordinator module initiates transaction requests by generating a coordination context, where the coordination context includes a transaction context, a coordination type, and an initiator supplemental address. The coordinator module includes a supplemental address handler for creating the initiator supplemental address that unique identifies the coordinator module and the associated pod. The coordinator module receives transaction responses, where the transaction response includes a coordination context. The coordinator module includes a transaction context checker to verify that the transaction response was not received in error, by comparing the received transaction context with a saved transaction context. The coordinator module includes a registration bridge that identifies an alternate coordinator module and alternate pod to process the transaction response if the transaction contexts do not match.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Shuo Zhang, Dian Guo Zou, Jing Jing Wei, Da Guang Sun, Yue Wang, Ping Mei
  • Publication number: 20240122936
    Abstract: The disclosure describes methods of synthesis of pyridazinone compounds as thyroid hormone analogs and their prodrugs. Preferred methods according to the disclosure allow for large-scale preparation of pyridazinone compounds having high purity. In some embodiments, preferred methods according to the disclosure also allow for the preparation of pyridazinone compounds in better yield than previously used methods for preparing such compounds. Also disclosed are morphic forms of a pyridazinone compound. Further disclosed is a method for treating resistance to thyroid hormone in a subject having at least one TR? mutation.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: D. Keith HESTER, II, Robert J. DUGUID, Martha J. KELLY, Anna CHASNOFF, Gang DONG, Edwin L. CROW, Lianhe SHU, Ping WANG, Duk Soon CHOI
  • Publication number: 20240126000
    Abstract: The technology of this application relates to a frontlight module and a display apparatus. The frontlight module is disposed on a side of a display panel. The frontlight module includes a light source, a light guide plate, and light guide dots. The light guide plate includes a first surface and a second surface that are disposed opposite to each other. The display panel is disposed facing the second surface. The light source is disposed on a side surface of the light guide plate. A plurality of light guide dots are disposed on the first surface or the second surface of the light guide plate. Each light guide dot has a light guide surface disposed at an angle with respect to a surface of the light guide plate. Light is fully reflected and/or refracted on the light guide surfaces to propagate to the display panel.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 18, 2024
    Inventors: Jifeng Tan, Feng Liao, Qiang Wang, Xiaoshan Chen, Han Yin, Liang Yuan, Ping Pan
  • Publication number: 20240124409
    Abstract: The present application discloses a class of guaianolide sesquiterpene lactone derivatives and pharmaceutical use thereof. The guaianolide sesquiterpene lactone derivative or a pharmaceutically acceptable salt thereof is shown as general formula I. In the present application, a class of novel guaianolide sesquiterpene lactone derivatives are found by structural optimization with abundant natural ingredients such as parthenolide and dehydrocostus lactone as raw materials, which derivatives have good inhibitory activity on the activation of the NLRP3 inflammasome, and the chemical stability, water solubility and oral bioavailability of which are significantly improved, and it is verified by experiments that the derivatives have inhibitory effects on the activity of the NLRP3 inflammasome and have potential pharmaceutical applications.
    Type: Application
    Filed: November 26, 2023
    Publication date: April 18, 2024
    Applicant: NANJING UNIVERSITY OF CHINESE MEDICINE
    Inventors: Lihong HU, Jian LIU, Qi LV, Yang HU, Dong DONG, Ping WANG, Meng YANG
  • Publication number: 20240130141
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11961866
    Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Chi Wang, Chia-Ping Lai, Chung-Chuan Tseng
  • Publication number: 20240120460
    Abstract: The present disclosure discloses a blended ternary positive-electrode material, a preparation method thereof and a lithium ion battery, and relates to the field of lithium battery technologies. A temperature-sensitive precursor type material is taken as a raw material, a large-particle precursor, a small-particle precursor and lithium sources are presintered to obtain a first presintered material and a second presintered material, presintered materials and binders are then mixed, compacted and punctured to obtain a first to-be-sintered material block and a second to-be-sintered material block, the first to-be-sintered material block and the second to-be-sintered material block are loaded into a sagger together for primary sintering, and using a periphery-center regional mode or an upper-lower-layer distribution mode, the first presintered material is distributed at a periphery or an upper layer, and the second presintered material is distributed at a center or a lower layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 11, 2024
    Applicant: YIBIN LIBODE NEW MATERIAL CO., LTD
    Inventors: Weifeng FAN, Ping ZHANG, Shilin HOU, Bin ZHANG, Cheng LI, Changwang HAO, Zhengqiang WANG
  • Publication number: 20240115048
    Abstract: A lifting device of a display, is provided. The lifting device includes a stationary member, a lifting member, and an elastic module. The stationary member is suitable for being fixed to a vertical plane. The lifting member is slidably connected to the stationary member. The lifting member is suitable for being fixed to a back portion of the display. The lifting member is suitable for sliding relative to the stationary member between a first position and a second position lower than the first position. The elastic module is coupled between the stationary member and the lifting member. The elastic module is suitable for exerting a pulling force opposite to a gravity direction on the lifting member.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: AmTRAN TECHNOLOGY Co., Ltd.
    Inventors: Hung-Tse Wang, Chun-Ping Tai
  • Publication number: 20240120639
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Application
    Filed: August 10, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Patent number: 11956372
    Abstract: The present invention relates to a judgment method for edge node computing result trustworthiness based on trust evaluation, and belongs to the technical field of data processing. By means of the present invention, a security mechanism for trustworthiness of a computing result output by an industrial edge node is guaranteed, the industrial edge node is prevented from outputting error data, and attacks of false data of malicious edge nodes are resisted, it is guaranteed that trustworthy computing results not be tampered are input in the industrial cloud, and a site device is made to receive correct computing results rather than malicious or meaningless messages, thereby improving efficiency and security of industrial production.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 9, 2024
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Min Wei, Er Xiong Liang, Ping Wang
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: RE49940
    Abstract: A method of starting an electronic device includes: receiving a first wireless signal carrying a first identification data by a wireless receiver before the electronic device enters a normal operating state; comparing the first identification data with a valid data; obtaining an account name and a password according to the first identification data if the first identification data matches the valid data and logging in to an operating system with the account name and the password so as to allow the electronic device to enter the normal operating state; and not logging in to the operating system if the first identification data does not match the valid data.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 23, 2024
    Assignee: Getac Holdings Corporation
    Inventor: Chen-Ping Wang