Abstract: A liquid crystal phase shifter and a liquid crystal antenna are provided. The liquid crystal phase shifter includes a first substrate and a second substrate oppositely disposed; a liquid crystal layer disposed between the first substrate and the second substrate; a radio frequency connector; and a driving chip. A side of the second substrate adjacent to the first substrate includes a first conductive layer connected to a constant potential; a side of the first substrate adjacent to the second substrate includes a second conductive layer including a transmission electrode; the first substrate includes a first area bonded with a circuit board; and the radio frequency connector and the driving chip are both disposed in the first area and transmit signals through the circuit board.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: Described are chips for detecting a target in a sample including a microfluidic flow chamber comprising one or more flow channels having a capture surface and at least one micromixer. Described are methods of using this chip wherein targets are identified by total internal reflection fluorescence (TIRF).

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: A biodegradable film comprises from 1 wt % to 10 wt % of a first polyhydroxyalkanoate resin component, from 50 wt % to 90 wt % of a second polyhydroxyalkanoate resin component, and from 5 wt % to 48 wt % of a polybutylene adipate terephthalate resin. Specifically, the first poly(3-hydroxybutyrate-co-3-hydroxyhexanoate) resin contains a first mol % of 3-hydroxyhexanoate structural units, and the second poly(3-hydroxybutyrate-co-3-hydroxyhexanoate) resin contains a second mol % of 3-hydroxyhexanoate structural units, while the second mol % is higher than the first mol %, e.g., by 2-40 mol %, or 3-30 mol %, or 4-20 mol %.

Abstract: A multiple-lens optical fingerprint reader for reading fingerprints through a display has an image sensor integrated circuit with photosensor array(s); a spacer; and multiple lenses in a microlens array, each lens of multiple lenses focuses light arriving at that lens from a finger adjacent the display through the spacer to form an image on associated photosensors on a photosensor array of the integrated circuit. A method of verifying identity of a user includes illuminating a finger of the user with an OLED display; focusing light from the fingerprint through arrayed microlenses onto a photosensor array of an integrated circuit, reading the array to overlapping electronic fingerprint images; extracting features from the overlapping electronic fingerprint images or from a stitched fingerprint image, and comparing the features to features of at least one user in a library of features and associated with one or more fingers of one or more authorized users.

Abstract: A fail-safe input/output device includes an input/output circuit, a comparator circuit and a resistance adjustment circuit. The input/output circuit transmits a voltage having a higher voltage level in a first supply voltage and a second supply voltage to a first node to generate a driving voltage, wherein a first target level of the first supply voltage is lower than a second target level of the second supply voltage. The comparator circuit compares the first supply voltage with the second supply voltage to generate a control signal, and selectively transmits the first supply voltage to the first node according to the control signal. The resistance adjustment circuit adjusts a resistance between the first node and a second node according to the second supply voltage, wherein the input/output circuit transmits the second supply voltage to the first node via the second node.

Abstract: A touch-control panel and a touch-control displaying device, which relates to the technical field of touch control. In the present application, by providing the first carrier element, the first electrically conductive layer and the first shadow eliminating layer on the substrate, by blocking the first electrically conductive layer by using the first shadow eliminating layer, the reflectivity of the first electrically conductive layer is reduced, which reduces the pattern of the first electrically conductive layer being observed under intensive-light reflection.

Abstract: A method for modifying glycoproteins is provided. The present disclosure also provides a method for producing glycoprotein-payload conjugates, the conjugates produced thereby, and the use thereof.

Abstract: The present invention relates to a cross-network time synchronization method for industrial wireless network and TSN fusion, which belongs to the field of Industrial Internet, comprising the following steps: S1: conducting clock synchronization by a TSN module of a border gateway with a TSN switch of a TSN 2 in a slave clock state; S2: inside the border gateway, using the TSN module as a master clock of an industrial wireless module, and conducting clock synchronization by the industrial wireless module with the TSN module through a serial port; S3: conducting clock synchronization by a routing device in the industrial wireless network with the industrial wireless module of the border gateway through a beacon frame synchronization mode in the slave clock state, and conducting clock synchronization by the routing device as the master clock of a node device for the node device; S4: conducting clock synchronization by a terminal side conversion node in the slave clock state with the node device in the industrial

Abstract: A method of fabricating a heterostructure includes providing a substrate, and implementing a non-sputtered, epitaxial growth procedure at a growth temperature to form a wurtzite structure supported by the substrate. The wurtzite structure includes an alloy of a III-nitride material. The non-sputtered, epitaxial growth procedure is configured to incorporate a group IIIB element into the alloy of the III-nitride material. The growth temperature is at a level such that the wurtzite structure exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the wurtzite structure.

Abstract: Provided in the present disclosure are a display substrate and a display apparatus.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.

Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

Abstract: A battery enclosure to house a battery pack of an electric vehicle includes a bottom plate, a battery pack including multiple batteries or battery modules, a frame enclosure at least partially surrounding the battery pack, the frame enclosure connected with the bottom plate, the frame enclosure including at least a first side wall and a second side wall, and multiple cross members each extending between the first side wall and the second side wall. The battery enclosure includes a top plate configured to cover the multiple structural cross members and at least a portion of the battery pack. The top plate is connected with the frame enclosure and includes multiple ridges protruding from a top surface of the top plate, each ridge defining a channel extending parallel to the top surface of the top plate, and each channel configured to facilitate flow of a heat transfer medium through the channel.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.