Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250064000
    Abstract: The present invention provides an anti-insect culture medium, comprising a shaped medium having a plurality of pores interconnected to each other, and an anti-insect agent evenly dispersed and fixed in the pores; wherein the shaped medium comprises at least one culture medium solid, the anti-insect agent comprises an anti-insect ingredient, and the anti-insect agent is a sustained-release formulation. The anti-insect culture medium of the present invention can provide a long-term and complete anti-insect efficacy to plant roots. The present invention further provides an anti-insect method, which reduces the amount of anti-insect agents and avoids the inconvenience of regular application.
    Type: Application
    Filed: August 5, 2024
    Publication date: February 27, 2025
    Applicant: ROYAL BASE CORPORATION
    Inventor: Hao-Ping WANG
  • Patent number: 12233305
    Abstract: The application relates to a dumbbell which is convenient for adjusting a load. By arranging telescopic sleeves which can be telescopically adjusted in a handle of the dumbbell, a number of counterweights nested on the telescopic sleeves is controlled, thus achieving an easy adjustment of the load. By arranging a rotatable knob, the telescopic sleeves inside the handle are driven to act through a gear transmission. Meanwhile, due to a position limitation of a division bar of the dumbbell, the counterweights nested on the telescopic sleeves are prevented from sliding left and right, thus ensuring a firm coupling.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 25, 2025
    Assignee: ZHEJIANG KANGWANG INDUSTRY & TRADE CO., LTD
    Inventor: Ping Wang
  • Patent number: 12226816
    Abstract: Systems and methods for bending a material to a target resultant bending parameter using a bend forming tool are disclosed. The systems and methods receive values for parameters of properties of the material and of a bending process to be performed by the bend forming tool, creating or retrieving a calibration curve relating input bending parameter and resultant bending parameter based on the values from a database of calibration curves, determining a first springback compensated input bending parameter based on the target resultant bending parameter using the calibration curve, inputting the first springback compensated input bending parameter to the bend forming tool, and in a first step of bending the material, bending the material to the first springback compensated input bending parameter by applying the bending process using the bend forming tool.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 18, 2025
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Lu Huang, Hui-ping Wang, Bradley J Blaski, Joshua Lee Solomon, Blair E Carlson
  • Patent number: 12224482
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Patent number: 12220463
    Abstract: The present invention provides a cationic ?-cyclodextrin and a preparation method and uses thereof, as well as a cationic ?-cyclodextrin functionalized silver nanoparticles and a preparation method and uses thereof. The cationic ?-cyclodextrin of the present invention is introduced with an amine group and quaternary ammonium groups, while retaining the special structure and properties of cyclodextrin itself. The amine group contained in the structure plays a role in reducing and complexing Ag+ in the synthesis of AgNPs, and plays a certain role in stabilizing nanoparticles and forming a complex in combination with quaternary ammonium groups.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: February 11, 2025
    Assignee: Hubei University of Chinese Medicine
    Inventors: Junfeng Liu, Junfeng Zan, Ping Wang, Guohua Zheng, Laichun Luo, Cong Chang, Ke Yang
  • Patent number: 12221593
    Abstract: Bioactive coatings that include a base and a protein associated with the base for actively promoting the removal of organic stains are provided. In aspects, bioactive coatings that are stabilized against inactivation by weathering are provided including a base associated with a chemically modified enzyme, and, optionally a first polyoxyethylene present in the base and independent of the enzyme. The coatings are optionally overlayered onto a substrate to form an active coating facilitating the removal of organic stains or organic material from food, insects, or the environment.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: February 11, 2025
    Assignees: TOYOTA MOTOR CORPORATION, REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Andreas Buthe, Ping Wang, Songtao Wu, Hongfei Jia, Masahiko Ishii, Minjuan Zhang
  • Publication number: 20250048936
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Application
    Filed: October 17, 2024
    Publication date: February 6, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20250048648
    Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.
    Type: Application
    Filed: October 16, 2024
    Publication date: February 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
  • Publication number: 20250040149
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20250035718
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen -Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20250024955
    Abstract: A sofa with adjustable coupled headrest and backrest includes a base movably connected with a side panel and a coupling sheet for backrest hinged at the side panel, and a backrest assembly including a connection element of backrest with a front end hinged at a rear end of the side panel at an upper positionn and a connection rod of backrest with an upper end hinged at a rear end of the connection element of backrest, and with a lower end hinged at the coupling sheet for backrest, the base is provided with a drive member to switch a backrest frame to a lying position, and a coupling assembly for headrest configured to force the connection element for headrest to flip relative to a backrest skeleton is provided between the connection rod of backrest and the connection element for headrest.
    Type: Application
    Filed: May 8, 2024
    Publication date: January 23, 2025
    Inventors: Ping WANG, Sheng WANG, Luping SHI, Linlin WU, Jingbo NING
  • Publication number: 20250031218
    Abstract: A first node receives a first DCI, the first DCI comprising a first field, the first field indicating a minimum applicable scheduling offset; a minimum scheduling offset value set includes K1 candidate minimum scheduling offset values, the minimum applicable scheduling offset being one of the K1 candidate minimum scheduling offset values; the minimum scheduling offset value set is one of multiple candidate minimum scheduling offset value sets; determining the minimum scheduling offset value set from the multiple candidate minimum scheduling offset value sets depends on one of: a resource occupied by the first DCI; or a time-domain resource occupied by a channel or signal scheduled by the first DCI; or a reference signal resource QCL with a physical layer channel scheduled by the first DCI. This application improves the scheme for determining the minimum applicable scheduling offset to support cross-slot scheduling for various scenarios, including full-duplex scenarios.
    Type: Application
    Filed: July 15, 2024
    Publication date: January 23, 2025
    Applicant: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventors: Qi JIANG, Ping WANG, Xiaobo ZHANG
  • Patent number: 12207564
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: January 21, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Publication number: 20250022690
    Abstract: A ring of an edge ring assembly for an etching system and methods of using the ring are described. In some embodiments, the ring includes a top portion including a side surface defining an opening sized to receive a center portion of a substrate support supporting a semiconductor wafer, and the top portion has a first constant thickness. The ring further includes a bottom portion integrally connected to the top portion, and the bottom portion has a second constant thickness that is about 15 percent to about 115 percent of the first constant thickness.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Inventors: Yi Chiuan Xu, Shun-Ping Wang, Che-Cheng Chang, Chen-Hsiang Lu
  • Publication number: 20250023821
    Abstract: A joint optimization method for path selection and gate scheduling in time-sensitive networking comprises S1, a CNC finding a TSN topology, and abstracting same into a network directed graph; S2, a terminal device sending to a CUC a TSN connection request, and the CUC sending same to the CNC; S3, the CNC selecting K shortest paths as alternative paths; S4, the CNC selecting m preferred paths; S5, the CNC finding an optimal transmission path for a TT stream, and finding a proper transmission path for a non-TT stream; S6, CNC completing traversal; S7, configuring a gate control list for the optimal transmission path of each pair of terminal devices; and S8, the CNC encapsulating a computation result into a gate scheduling table, configuring the gate scheduling table to a TSN switch, and then sending a traffic transmission computation result to the TSN terminal device.
    Type: Application
    Filed: May 7, 2022
    Publication date: January 16, 2025
    Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Min WEI, Xingbin FANG, Mengfei YOU, Chengjie HUO, Ping WANG, Wei XU
  • Publication number: 20250024464
    Abstract: The first node receives a first DCI scheduling K1 cells; at least 2 cells among the K1 cells respectively correspond to subcarrier spacings that are unequal, K1 being a positive integer greater than 1; the first minimum applicable scheduling offset is indicated via a physical layer dynamic signaling in a first slot; a first cell is one of the K1 cells, and the first cell is different from a cell to which the physical layer dynamic signaling belongs, the first minimum applicable scheduling offset applying to the first cell from a second slot of the first cell; the second slot depends on the first slot and a first offset value, the first offset value being related to both a subcarrier spacing corresponding to the first cell and a subcarrier spacing corresponding to the cell to which the physical layer dynamic signaling belongs. This application is for the effective time.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 16, 2025
    Applicant: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventors: Qi JIANG, Ping WANG, Zheng LIU, Xiaobo ZHANG
  • Publication number: 20250019566
    Abstract: Bioactive coatings that are stabilized against inactivation by weathering are provided including a base associated with a chemically modified enzyme capable of enzymatically degrading a component of an organic stain, optionally a lipase or a lysozyme, and optionally a first polyoxyethylene present in the base and independent of the enzyme. The coatings are optionally overlayered onto a substrate to form an active coating facilitating the removal of organic stains or bacterial organic material.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 16, 2025
    Inventors: Hongfei Jia, Ping Wang, Liting Zhang, Andreas Buthe, Xueyan Zhao, Songtao Wu, Masahiko Ishii, Minjuan Zhang
  • Patent number: 12201032
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 14, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20250015023
    Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Chung-Hsing Kuo, Chun-Ting Yeh, Chuan-Lan Lin, Yu-Ping Wang, Yu-Chun Chen
  • Publication number: 20250010699
    Abstract: A rechargeable energy storage system for a vehicle including a bottom shear plate and a side enclosure having a bottom end connected to the bottom shear plate. A top shear plate is connected to a top end of the side enclosure and a plurality of battery cells are suspended from a bottom of the top shear plate by corresponding mating features that secure the plurality of cells to the top shear plate.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Lu HUANG, Hui-ping Wang, Dohyun Leem, Joshua Lee Solomon, Derek Frei Lahr, Blair E. Carlson