Abstract: A method for vehicle motion forecasting includes the following steps. A lane graph structure is generated according to a raw map data. Multiple occupancy flow graphs which are homogeneous to data format of the lane graph structure are established according to trajectory data of a plurality of vehicles in multiple consecutive frames and the lane graph structure. Multiple temporal edges between the occupancy flow graphs are established according to the trajectory data of the vehicles in the consecutive frames to construct a temporal occupancy flow graph. Feature aggregation is performed on the temporal occupancy flow graph to generate multiple updated node features, and a motion forecasting of an ego-vehicle is generated according to the updated node features.

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A user equipment device may determine whether to power down one or more components based at least on a scheduling parameter that includes an indication of cross-slot scheduling. The device may power down the one or more components prior to decoding control information during a slot for which the scheduling parameter indicates that cross-slot scheduling is in place.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A solid electrolyte three-electrode electrochemical test device comprises a housing, a working electrode, a counter electrode, a reference electrode, a first conductive structure, a second conductive structure, a third conductive structure, and a solid electrolyte layer. The housing comprises a groove and a first through hole located at a bottom of the groove. The reference electrode is insulated from the counter electrode. The first conductive structure and the working electrode are stacked with each other, and the working electrode and at least a part of the first conductive structure are located in the first through hole. The solid electrolyte layer, the counter electrode, the reference electrode, the second conductive structure and the third conductive structure are located in the groove, and the first conductive structure, the working electrode, the solid electrolyte layer, the counter electrode, and the second conductive structure are sequentially stacked and located coaxially with each other.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: Provided are methods and compositions for self-cleaning that include a digestive protein capable of decomposing stain forming molecules, a substrate applied to a solid surface, and a linker moiety bound to an outer surface of said substrate and an active group of said digestive protein, said linker moiety between said protein and said substrate and covalently linking said protein to a surface of said substrate by an amide bond, the linker moiety between a free amine of said protein and said outer surface of said substrate wherein the digestive protein forms a layer on a surface of said substrate such that the digestive protein is surface exposed for reaction with a stain.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Abstract: Bioactive coatings that include a base and a protein associated with the base for actively promoting the removal of organic stains are provided. In aspects, bioactive coatings that are stabilized against inactivation by weathering are provided including a base associated with a chemically modified enzyme, and, optionally a first polyoxyethylene present in the base and independent of the enzyme. The coatings are optionally overlayered onto a substrate to form an active coating facilitating the removal of organic stains or organic material from food, insects, or the environment.

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

Abstract: In general, the disclosure is directed to bulk iron-nitride materials having a polycrystalline microstructure having pores including a plurality of crystallographic grains surrounded by grain boundaries, where at least one crystallographic grain includes an iron-nitride phase including any of a body centered cubic (bcc) structure, a body centered tetragonal (bct), and a martensite structure. The disclosure further describes techniques producing a bulk iron-nitride material having a polycrystalline microstructure, including: melting an iron source to obtain a molten iron source; fast belt casting the molten iron source to obtain a cast iron source; cooling and shaping the cast iron source to obtain a bulk iron-containing material having a body-centered cubic (bcc) structure; annealing the bulk iron-containing material at an austenite transformation temperature and subsequently cooling the bulk iron-containing material; and nitriding the bulk iron-containing material to obtain the bulk iron-nitride material.

Abstract: A power detector device includes a voltage generator circuit, a reference circuit, a level hold circuit and a comparator circuit. The voltage generator circuit generates a bias voltage and a detection voltage according to a power supply voltage. The reference circuit generates a first reference voltage according to the power supply voltage. The level hold circuit selectively transmits the first reference voltage to a node according to the bias voltage, outputs a second reference voltage via the node, and holds a level of the second reference voltage after stopping transmitting the first reference voltage to the node. The comparator circuit compares the second reference voltage with the detection voltage to generate a power detection signal.

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.