Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12348114
    Abstract: A locking apparatus comprises a sliding member, and a first memory alloy wire configured to engage the sliding member to exert a first force to move the sliding member in a first sliding direction to a locked position when electrical energy is applied to the first memory alloy wire. The locking apparatus further comprises a second memory alloy wire configured to exert a second force to engage the sliding member to move the sliding member in a second sliding direction to an unlocked position when electrical energy is applied to the second memory alloy wire. The apparatus further comprises a position limiting structure. When the sliding member is moved to the locked position, the position limiting structure holds the sliding member at the locked position. When the sliding member is moved to the unlocked position, the position limiting structure holds the sliding member at the unlocked position.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: July 1, 2025
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Zhenpo Yang, Xin Sun, Ping Wang, Jianda Qiu
  • Publication number: 20250212420
    Abstract: A semiconductor structure includes a substrate having a memory device region covered by a first dielectric layer, a memory stack structure on the first dielectric layer, an insulating layer conformally covering the memory stack structure and the first dielectric layer, a second dielectric layer on the insulating layer, an etching stop layer on the second dielectric layer, a third dielectric layer on the etching stop layer, and a second interconnecting structure through the third dielectric layer, the etching stop layer and the insulating layer to contact a top surface of the memory stack structure. The insulating layer directly contacts a bottom surface of the etching stop layer and partially covers a bottom surface and a lower sidewall of the second interconnecting structures.
    Type: Application
    Filed: March 12, 2025
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 12338536
    Abstract: A method may include annealing a material including iron and nitrogen in the presence of an applied magnetic field to form at least one Fe16N2 phase domain. The applied magnetic field may have a strength of at least about 0.2 Tesla (T).
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: June 24, 2025
    Assignee: Regents of the University of Minnesota
    Inventors: Michael P. Brady, Orlando Rios, YanFeng Jiang, Gerard M. Ludtka, Craig A. Bridges, Jian-Ping Wang, Xiaowei Zhang, Lawrence F. Allard, Edgar Lara-Curzio
  • Publication number: 20250201731
    Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress tuning structure and a first bonding structure. The stress tuning structure is disposed on the first substrate. The stress tuning structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The first bonding structure is disposed on the stress tuning structure. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate. The second bonding structure is bonded with the first bonding structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-An Shih, Che-Wei Tsai, Da-Jun Lin, I-Ming Tseng, Chung-Sung Chiang, Yu-Chun Chen, Yu-Ping Wang
  • Publication number: 20250200698
    Abstract: Disclosed are a system-on-chip-based image processing method, a device, and a storage medium. The method includes: determining abnormal information generated during processing a first image data frame by a plurality of image processing modules in the system-on-chip and path configuration information corresponding to the plurality of image processing modules; determining an abnormal module that generates the abnormal information and an initial handling strategy used to address the abnormal information; determining a target to-be-processed module from the plurality of image processing modules based on the abnormal module, the initial handling strategy, and the path configuration information; and processing the target to-be-processed module based on the initial handling strategy to obtain the processed target to-be-processed module, so as to continue to process a second image data frame by using the processed target to-be-processed module.
    Type: Application
    Filed: February 27, 2025
    Publication date: June 19, 2025
    Applicant: BEIJING HORIZON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Lingfang JIN, Ping WANG, Zengyuan LOU, Kaikai SUN, Youjin SHEN
  • Publication number: 20250202078
    Abstract: A battery cell includes a stack including C cathode electrodes each including a cathode current collector, a cathode active layer, and an external tab, A anode electrodes each including an anode current collector, an anode active layer, and an external tab, S separators, and an internal terminal including a slot. The external tabs of one of the C cathode electrodes and the A anode electrodes extend through the slot and are welded in the slot, the slot is open-ended and defines a first leg and a second leg on opposite sides of the slot, and each of the first leg and the second leg is tapered where a first width of the slot at an open end of the slot is greater than a second width of the slot at a closed end of the slot.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Masoud MOHAMMADPOUR, Junjie Ma, Teresa Jean Rinker, Andrew Hromadka, Hui-ping Wang
  • Publication number: 20250202079
    Abstract: A battery cell includes a stack including C cathode electrodes each including a cathode current collector, a cathode active layer, and an external tab, A anode electrodes each including an anode current collector, an anode active layer, and an external tab, and S separators, an internal terminal including a first slot, wherein the external tabs of one of the C cathode electrodes and the A anode electrodes extend through the first slot, and a cover plate in contact with the external tabs of the one of the C cathode electrodes and the A anode electrodes extending through the first slot. The external tabs of the one of the C cathode electrodes and the A anode electrodes extending through the first slot are folded and laser welded between the cover plate and a surface of the internal terminal.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Teresa Jean RINKER, Masoud Mohammadpour, Junjie Ma, Hui-ping Wang
  • Publication number: 20250204270
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: March 2, 2025
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20250204272
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: March 6, 2025
    Publication date: June 19, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20250194436
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20250194293
    Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
    Type: Application
    Filed: January 24, 2025
    Publication date: June 12, 2025
    Inventors: Shih-Yuan WANG, Shih-Ping Wang
  • Publication number: 20250194230
    Abstract: A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.
    Type: Application
    Filed: January 8, 2024
    Publication date: June 12, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Yu-Ping Wang, I-Ming Tseng, Yu-Chun Chen, Yi-An Shih
  • Patent number: 12326411
    Abstract: According to one embodiment, a sensor includes a detection device and a circuit portion. The detection device includes a first detection portion and a second detection portion. The first detection portion includes a first detection element. The first detection element includes a first conductive member and a first detection member. The second detection portion includes a second detection element. The second detection element includes a second conductive member and a second detection member. The circuit portion is configured to execute a first detection portion operation for outputting a first detection result corresponding to a first detection value based on the first detection member when a first current is supplied to the first conductive member. In a case where a first evaluation value is not within a first range, the circuit portion is configured to execute a second detection portion operation by the second detection portion.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: June 10, 2025
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Kurui, Hiroaki Yamazaki, Yosuke Akimoto, Ping Wang, Fumitaka Ishibashi, Yumi Hayashi
  • Publication number: 20250179577
    Abstract: A screening method of an autolysosome gene C10ORF10 for regulating fat function of obese patients is provided, including collecting subcutaneous and visceral adipose tissues from people with different metabolic conditions and different BMIs, followed by transcriptome sequencing analysis; dividing specimens from people with normal metabolism into two groups of BMI<25 kg/m2 and BMI>30 kg/m2, comparing the two groups in terms of expression differences of autolysosome-related genes in subcutaneous and visceral adipose tissues, screening out differential genes; analyzing and observing several autolysosome-related genes in terms of differential expressions existed in the subcutaneous and visceral adipose tissues of the two groups of BMI<25 kg/m2 and BMI>30 kg/m2, where a gene with a greatest expression difference is C10ORF10.
    Type: Application
    Filed: September 16, 2024
    Publication date: June 5, 2025
    Inventors: Yujie Deng, Ping Wang, Qing Yu, Yajun Jing, Xiaoxia Wang, Shumin Xu
  • Publication number: 20250181335
    Abstract: A method, computer program product, and computer system are provided for assuring quality of machine translations based on large language models. Data corresponding to an input in a first language is received for machine translation. The received data is translated from the first language to a second language through a translation engine. A confidence value associated with the translated data is determined. The translation is revised with executable source code based on the confidence value being greater than a threshold value. Otherwise, the translation is revised based on sending a prompt to a large language model based on the confidence value being less than the threshold value.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 5, 2025
    Inventors: YUAN JIN, XI XI LIU, Li ping Wang, Brian Robert Matthiesen, Wei Sun
  • Publication number: 20250185257
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, the first SOT layer and the second SOT layer are made of same material.
    Type: Application
    Filed: February 10, 2025
    Publication date: June 5, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang
  • Publication number: 20250183515
    Abstract: A three dimensional (3D) Integrated Circuit (IC) package is provided. The 3D IC package includes a first IC die having a first substrate at a back side of the first IC die and a second IC die stacked at the back side of the first IC die and facing the first substrate. The 3D IC further includes a Through Silicon Via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV. A protection module is fabricated in the first substrate. The protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Application
    Filed: February 10, 2025
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Patent number: 12322670
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Publication number: 20250176205
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a semiconductor barrier layer and a gate electrode. The semiconductor barrier layer is disposed above the substrate. The gate electrode is disposed above the semiconductor barrier layer and has a first gate barrier layer and a second gate barrier layer. The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The work function of the first gate barrier layer is greater than that of the semiconductor barrier layer, and the work function of the second gate barrier layer is greater than that of the first gate barrier layer.
    Type: Application
    Filed: August 27, 2024
    Publication date: May 29, 2025
    Inventors: Jui-Lun CHUNG, Sheng-Ping WANG
  • Publication number: 20250169097
    Abstract: A device includes a substrate, a heterostructure supported by the substrate, the heterostructure including a semiconductor layer supported by the substrate, and a ferroelectric III-nitride alloy layer supported by the semiconductor layer, the ferroelectric III-nitride alloy layer including a Group IIIB element, and first and second contacts in electrical communication with the ferroelectric III-nitride alloy layer and the semiconductor layer, respectively, such that a polarity of a poling voltage applied across the first and second contacts establishes a state of ferroelectric polarization of the ferroelectric III-nitride alloy layer
    Type: Application
    Filed: February 23, 2023
    Publication date: May 22, 2025
    Inventors: Ding Wang, Ping Wang, Zetian Mi