Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240429332
    Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Inventors: Shih-Yuan WANG, Shih-Ping WANG
  • Publication number: 20240429306
    Abstract: A method includes of fabricating a heterostructure includes growing epitaxially, in a growth chamber, a first semiconductor layer of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate, and, after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy.
    Type: Application
    Filed: October 24, 2022
    Publication date: December 26, 2024
    Inventors: Zetian Mi, Ping Wang, Ding Wang
  • Publication number: 20240429093
    Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.
    Type: Application
    Filed: July 21, 2023
    Publication date: December 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Kai-Kuang Ho, Chuan-Lan Lin, Yu-Ping Wang, Chu-Fu Lin, Yi-Feng Hsu, Yu-Jie Lin
  • Patent number: 12173915
    Abstract: The present disclosure provides an air conditioner defrosting control method and device, and a storage medium and an air conditioner. The control method includes: setting a target discharge temperature of a compressor and an initial opening degree of a throttle device when an air conditioner performs defrosting according to an outdoor ambient temperature when the air conditioner meets a defrosting condition and enters a defrosting mode; controlling a defrosting operation of the air conditioner according to the target discharge temperature of the compressor and the initial opening degree of the throttle device; and controlling the air conditioner to exit the defrosting mode when a temperature of an outdoor heart exchanger of the air conditioner reaches a set temperature value.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 24, 2024
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Zhiqiang Li, Dandan Lyu, Jiancheng Li, Yulong Liang, Weishuang Liu, Qiuyu Zhang, Ping Wang
  • Publication number: 20240423095
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20240408177
    Abstract: The present disclosure provides IL-10 muteins and use of IL-10 muteins in fusion proteins. The IL-10 mutein or the fusion protein comprise one or more substitution on amino acids in position 104, position 107, and a combination thereof, relative to amino acids of wild-type IL-10. Advantageously, the IL-10 mutein or the fusion protein thereof are provided with reduced aggregation potency during purification and extended half-life.
    Type: Application
    Filed: October 6, 2022
    Publication date: December 12, 2024
    Inventors: Hung-Kai CHEN, Po-Hao Chang, Wei Huang, Jing-Yi Huang, Pandelakis Andreas KONI, Tsung-Hao CHANG, Shih-Rang YANG, Yin-Ping WANG
  • Publication number: 20240410869
    Abstract: According to one embodiment, a sensor includes a sensor section and a circuit section. The sensor section includes a first element portion including a first resistance element and a first conductive member, and a second element portion including a second resistance element. The circuit section includes a detector and a controller, and is configured to perform a first operation. The controller controls a first power in the first operation based on a second signal corresponding to a second resistance of the second resistance element. In the first operation: the controller supplies the first power to the first conductive member to increase a first temperature of the first element section; and the detector outputs a detected value corresponding to a difference between the second signal and a first signal corresponding to a first resistance of the first resistance element in a first state in which the first temperature is raised.
    Type: Application
    Filed: February 21, 2024
    Publication date: December 12, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ping WANG, Masayuki MATSUTAKE, Hiroaki YAMAZAKI, Yoshihiko KURUI, Yosuke AKIMOTO
  • Publication number: 20240413960
    Abstract: A first node receives a target signaling, the target signaling indicating at least one symbol of first type, the at least one symbol of the first type including a downlink symbol for uplink transmission in a first sub-band that is indicated by TDD UL-DL configuration; and transmits a first signal; the first signal comprises a first sub-signal and a second sub-signal, the first sub-signal and the second sub-signal being two hops for the first signal, respectively; the first signal occupies a target symbol set in time domain; a starting RB occupied by the second sub-signal is a target RB, where a frequency-domain location of the target RB depends on a first integer, a distribution of the symbols of the first type in the target symbol set is used to determine the first integer. This application improves the uplink frequency hopping transmission procedure, and improves the anti-interference ability of signals.
    Type: Application
    Filed: May 29, 2024
    Publication date: December 12, 2024
    Applicant: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventors: Qi JIANG, Ping WANG, Xiaobo ZHANG
  • Publication number: 20240413150
    Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company , Ltd.
    Inventors: Chieh-Ping Wang, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui
  • Patent number: 12162901
    Abstract: The present invention provides N-acetyl derivatives of sialic acids, including N-acetyl derivatives of Neu5Ac and Neu5Gc. Methods for preparing related precursors and a variety of sialosides are also disclosed.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 10, 2024
    Assignee: The Regents of the University of California
    Inventors: Xi Chen, An Xiao, Anoopjit Kooner, Abhishek Santra, Ajit Varki, Hai Yu, Lee-Ping Wang, Wanqing Li
  • Publication number: 20240405332
    Abstract: A battery system includes N hollow battery cells, each including an enclosure including a top surface, a bottom surface, and a side wall; a hollow center tube including a side wall and a cavity enclosed by the side wall, and a roll including electrode and separator layers arranged between an outer surface of the hollow center tube and the enclosure. The hollow center tube passes through at least one of the top surface and the bottom surface of the enclosure. A battery heat exchange system includes a first fluid channel including N ports configured to at least one of supply fluid to and receive fluid from at least one end of the hollow center tube of the N hollow battery cells.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Hui-ping WANG, Lu HUANG, Fang DAI, Guangze LI, Mei CAI
  • Publication number: 20240401963
    Abstract: A trajectory prediction apparatus is configured to execute the following operations. A reference path line is selected from multiple path lines of a scene based on multiple first trajectory coordinates of an object, wherein the first trajectory coordinates and the path lines correspond to a first coordinate system. The first trajectory coordinates of the first coordinate system are transformed into multiple second trajectory coordinates corresponding to a second coordinate system, wherein the second trajectory coordinates indicate relationships of the object corresponding to the reference path line. A predicted trajectory of the object is generated based on the second trajectory coordinates by using a prediction model.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Inventors: Lu-Yao YE, Zi-Kang ZHOU, Jian-Ping WANG, Yung-Hui LI, Nien-Yi JAN, Yi-Rong LIN, Yen-Cheng LIN
  • Publication number: 20240405319
    Abstract: A hollow battery cell includes an enclosure including a top surface, a bottom surface, and side walls. A hollow center tube includes a side wall passing through at least one of the top surface and the bottom surface of the enclosure. A roll includes one or more electrodes and separators arranged between an outer surface of the hollow center tube and the enclosure.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Fang DAI, Hui-ping WANG, Lu HUANG, Guangze LI, Mei CAI
  • Publication number: 20240392200
    Abstract: A grading system and an application of a hydrogenation catalyst and a grading method of the hydrogenation catalyst are provided. The system contains M hydrogenation catalysts sequentially filled in a material flow direction. An R value of an Nth hydrogenation catalyst is not less than an R value of an (N?1)th hydrogenation catalyst, and the R value of at least one Nth hydrogenation catalyst is greater than the R value of the (N?1)th hydrogenation catalyst. N is an integer greater than 2 and not greater than M; the R value is a ratio of molar content of the VIII group metal element in the hydrogenation catalyst characterized by an X-ray photoelectron spectrum to weight content of the VIII group metal element in terms of oxides in the hydrogenation catalyst characterized by an X-ray fluorescence spectrum. The hydrogenation catalysts having different surface nickel atom concentrations are used for grading, thereby improving denitrification and the hydrogenation saturation performance of a catalyst system.
    Type: Application
    Filed: October 24, 2022
    Publication date: November 28, 2024
    Inventors: Zhanlin YANG, Sijia DING, Yi LIU, Shaozhong PENG, Huigang WANG, Hong JIANG, Jifeng WANG, Fangzhao WANG, Ping WANG
  • Publication number: 20240397018
    Abstract: Disclosed are a method for synchronizing images from multiple channels, a computer readable storage medium, and an electronic device. The method includes: determining, from at least two image transmission channels, target image data corresponding to a target image transmission channel at a preset timepoint; determining a mounting status of a frame identifier of the target image data; determining integrity information of the target image data based on the mounting status; generating the frame identifier of the target image data based on the integrity information; and generating, based on the frame identifier, a to-be-output image corresponding to each image transmission channel in the channels, outputting the to-be-output image.
    Type: Application
    Filed: May 20, 2024
    Publication date: November 28, 2024
    Applicant: Horizon Journey (Hangzhou) Technology Co., Ltd.
    Inventor: Ping WANG
  • Publication number: 20240390534
    Abstract: A sterilization and deodorization waste container includes an isolation chamber provided on an inner side of a container lid and a dual-band ultraviolet lamp tube installed in the isolation chamber. The dual-band ultraviolet lamp tube is capable of simultaneously generating a direct ultraviolet light wave and an ozone ultraviolet light wave. The isolation chamber includes a reflector housing having a light transmitting window facing an inner cavity of a container body. The dual-band ultraviolet lamp tube is controlled by a control circuit to turn on to generate the ultraviolet light rays into an inner cavity of the container body while the container lid is closed and to turn off to stop generating the ultraviolet while the container lid is opened.
    Type: Application
    Filed: April 14, 2024
    Publication date: November 28, 2024
    Applicants: Fujian Nashida Electronic Incorporated Company, Nine Stars (U.S.A.) Inc.
    Inventor: Shi Ping Wang
  • Publication number: 20240395921
    Abstract: A device includes a substrate and a semiconductor heterostructure supported by the substrate. The semiconductor heterostructure includes a first semiconductor layer supported by the substrate and including a first III-nitride semiconductor material, and a second semiconductor layer supported by the first semiconductor layer and including a second III-nitride semiconductor material. The second III-nitride semiconductor material includes scandium. The first and second semiconductor layers are nitrogen-polar.
    Type: Application
    Filed: August 24, 2022
    Publication date: November 28, 2024
    Inventors: Zetian Mi, Ping Wang, Ding Wang, Elaheh Ahmadi
  • Publication number: 20240391022
    Abstract: A system for joining a first part and a second part together with a weld structure. The system includes: a welding element configured to form the weld structure between the first part and the second part; and a control module configured to operate the welding element to form the weld structure. The weld structure includes: a first curved end; a second curved end; a connecting portion connecting the first curved end and the second curved end; a first curved crown spaced apart from the first curved end and concentric with the first curved end; and a second curved crown spaced apart from the second curved end and concentric with the second curved end. The first curved end, the second curved end, and the connecting portion are between the first curved crown and the second curved crown.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Inventors: Junjie MA, Ying LU, Hui-ping WANG, Joshua Lee SOLOMON, Baixuan YANG
  • Patent number: 12156478
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: November 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20240385678
    Abstract: Systems and methods for managing power consumption of device subsystems include a device which maintains one or more constraint metric tables for applications executable on the device. Each of the one or more constraint metric tables may specify respective power levels for subsystems of the device according to a respective application or an application type of the respective application. The device may determine to operate the device at a reduced power level for a first application, based on a condition for the device satisfying at least one of a thermal threshold criterion or a power threshold criteria when the device operates at full power level. The device may apply a constraint metric responsive to determining to operate at the reduced power level, to cause a subset of the plurality of subsystems to adjust a power consumption level according to a first constraint metric table corresponding to the first application.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Applicant: Meta Platforms Technologies, LLC
    Inventors: Siddharth RAY, Ping WANG, Achaleshwar SAHAI, Xiaodi ZHANG, Neeraj POOJARY, Dong ZHENG, Guoqing LI, Shivank NAYAK, Madhusudan Kinthada VENKATA, Swaminathan BALAKRISHNAN