Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250166997
    Abstract: The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.
    Type: Application
    Filed: December 13, 2023
    Publication date: May 22, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ping Wang, Chuan-Lan Lin, Chu-Fu Lin, Teng-Chuan Hu, Kun-Ju Li
  • Publication number: 20250169150
    Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Publication number: 20250151897
    Abstract: A sliding rail device includes a first rail, a second rail and two supporting units. The first rail includes a first base wall and two first side walls cooperating with the first base wall to define a first passage. The first base wall has two engaging slots respectively adjacent to the first side walls. The second rail engages the first passage, is movable relative to the first rail, and includes a second base wall and two second side walls. The supporting units respectively and movably engage the engaging slots, and respectively and slidably abut against the first side walls and the second side walls. During movement of the second rail relative to the first rail, the supporting units are driven to respectively move along the engaging slots, and to move toward each other to tighten abutment of the supporting units against the second side walls.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 15, 2025
    Applicant: FOSITEK CORPORATION
    Inventors: Chun-Han LIN, Che-Wei Chang, Jia-Wei Pan, Hao-Ping Wang
  • Publication number: 20250158203
    Abstract: A cell module bracket is provided. The cell module bracket includes a base and a top cover. The base and the top cover are connected to each other through a lifting assembly, and the lifting assembly is configured for adjusting the height of the top cover. Each of the base and the top cover is formed with multiple fixing grooves, and the multiple fixing grooves of the base are in one-to-one correspondence to the multiple fixing grooves of the top cover. Each of the fixing grooves is provided with a clamping assembly disposed therein. The clamping assembly includes multiple clamping parts uniformly distributed around a cell. A clamping space for fixing the cell is formed among the clamping parts, and each of the clamping parts is connected with an adjusting assembly. A cell module is provided. The cell module includes the cell module bracket.
    Type: Application
    Filed: May 23, 2024
    Publication date: May 15, 2025
    Applicant: ZHEJIANG UNIVERSITY OF SCIENCE & TECHNOLOGY
    Inventors: Youming TANG, Songfeng ZHONG, Yi ZHANG, Ping WANG
  • Publication number: 20250145026
    Abstract: A multifunctional unified structure thermal plate and system for supporting a plurality of battery cells included as part of a high voltage battery pack. The plate may include a bottom plate and a plurality of crossbeams configured for supporting the battery cells, with the bottom plate and the crossbeams together being from as a monolithic, one-piece structure.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Joel S. Hooton, Joshua L. Solomon, Hui-Ping Wang, Lu Huang, Xiaoling Chen
  • Publication number: 20250149758
    Abstract: A battery cell including a stack and a first internal terminal. The stack includes: C cathode electrodes each including a cathode current collector, a cathode active layer arranged on the cathode current collector, and an external connector extending from the cathode current collector; A anode electrodes each including an anode current collector, an anode active layer arranged on the anode current collector, and an external connector extending from the anode current collector; and S separators, where C, A, and S are integers greater than one. Each one of the external connectors, of one of the C cathode electrodes and the A anode electrodes, includes a first tab and a second tab extending farther than the first tab, the second tabs are folded onto the first tabs, and the first internal terminal is laser welded onto the second tabs.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Masoud MOHAMMADPOUR, Junjie MA, Hui-ping WANG, Teresa Jean RINKER, Vincent Edward HERRMAN
  • Publication number: 20250149334
    Abstract: A method of fabricating a heterostructure includes growing epitaxially, in a growth chamber, a first semiconductor layer of the heterostructure, the first semiconductor layer including a first III-nitride semiconductor material, the first semiconductor layer being supported by a substrate, after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer including a second III-nitride semiconductor material, and between growing the first semiconductor layer and growing the second semiconductor layer, controlling an extent to which a eutectic layer disposed on the first semiconductor layer is consumed to control a lattice polarity of the second semiconductor layer
    Type: Application
    Filed: February 13, 2023
    Publication date: May 8, 2025
    Inventors: Ping Wang, Ding Wang, Zetian Mi
  • Patent number: 12291567
    Abstract: Disclosed herein are anti-GM-CSF antibodies capable of binding to human GM-CSF and blocking its biological activities. Also provided herein are pharmaceutical compositions comprising the anti-GM-CSF antibodies and therapeutic and diagnostic uses of such antibodies.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: May 6, 2025
    Assignee: Elixiron Immunotherapeutics (Hong Kong) Limited
    Inventors: Cheng-Lun Ku, Yu-Fang Lo, Han-Po Shih, Jing-Ya Ding, Pei-Han Chung, Yin-Ping Wang
  • Patent number: 12290005
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: May 30, 2024
    Date of Patent: April 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Publication number: 20250129811
    Abstract: A weldment assembly includes a first component and a second component configured to be coupled to the first component. Additionally, the first component and the second component are coupled through a first linear stitch and a second linear stitch disposed parallel to the first linear stitch.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: GM Global Technology Operations LLC
    Inventors: Ying Lu, Junjie Ma, Hui-Ping Wang, Mitchell Poirier, Scott A. Hooker
  • Publication number: 20250132440
    Abstract: A battery casing includes a first portion including a first planar portion and a bottom portion and a second portion having a second planar portion, a first side portion, and a second side portion, the first portion and the second portion configured to be welded together at (i) a first butt joint extending along the first side portion to join the first side portion to the first planar portion and to the bottom portion at the first side portion, (ii) a second butt joint extending along the second planar portion to join the second planar portion to the bottom portion at the second planar portion, and (iii) a third butt joint extending along the second side portion to join the second side portion to the first planar portion and to the bottom portion at the second side portion.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: GM Global Technology Operations LLC
    Inventors: William P. Payne, Hui-Ping Wang, Vivian Vasquez, Lu Huang
  • Patent number: 12283485
    Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Wan-Hsien Lin, Chieh-Ping Wang, Tai-Chun Huang, Chi On Chui
  • Patent number: 12282074
    Abstract: The present invention relates to the technical field of maglev transportation, specifically revealing a method and apparatus for measuring magnetic field intensity in high-temperature superconducting maglev transportation systems.
    Type: Grant
    Filed: April 25, 2024
    Date of Patent: April 22, 2025
    Assignee: Southwest Jiaotong University
    Inventors: Rong Chen, Ping Wang, Tao Lv, Jingmang Xu, Zhou Xu, Kai Liu, Min Xue
  • Patent number: 12280138
    Abstract: The present invention provides a Bletilla dedifferentiated cell extract by carbon dioxide supercritical extraction, which has triple cosmetic efficacies of whitening, anti-oxidation and anti-wrinkling, and the advantages of low skin irritation potential. The present invention further provides a method for whitening, anti-oxidation and anti-wrinkling by applying the extract by carbon dioxide supercritical extraction, and a cosmetic comprising the same so as to meet all the skin cosmetic needs of consumers in an all-round way.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 22, 2025
    Assignee: CHLITINA INTELLIGENCE LIMITED
    Inventors: Ruei-Ting Wang, Yi-Cian Lai, Wei-Ping Wang
  • Patent number: 12284812
    Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
    Type: Grant
    Filed: April 16, 2024
    Date of Patent: April 22, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Publication number: 20250123397
    Abstract: An image capture system includes a light detection and ranging (LIDAR) device which captures images of an environment while rotating and a plurality of cameras, disposed separately from the LIDAR device, each including a rolling shutter sensor and each capturing images of the environment. The plurality of cameras include a first camera disposed to face in a first direction and a second camera disposed to face in a second direction. A time at which the first camera captures a first image is synchronized with a time at which the LIDAR device captures a second image when the LIDAR device rotates to face in the first direction, and a time at which the second camera captures a third image is synchronized with a time at which the LIDAR device captures a fourth image when the LIDAR device rotates to face in the second direction.
    Type: Application
    Filed: October 31, 2022
    Publication date: April 17, 2025
    Inventors: David Martin, Li-Ping Wang
  • Publication number: 20250125150
    Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.
    Type: Application
    Filed: December 26, 2024
    Publication date: April 17, 2025
    Inventors: Ting-Gang Chen, Wan-Hsien Lin, Chieh-Ping Wang, Tai-Chun Huang, Chi On Chui
  • Patent number: 12279016
    Abstract: An audio mixing method for network streaming includes the steps of establishing a network streaming connection between the first end and the second end, generating a text voiced audio signal based on a trigger signal by the first end, mixing a play signal and the text voiced audio signal into a play signal with the text voiced audio signal, in the state of the network streaming connection, transmitting the play signal with text voiced audio signal to the second end, and the play signal with text voiced audio signal is played by the second end.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: April 15, 2025
    Assignee: AVERMEDIA TECHNOLOGIES, INC.
    Inventor: Fu-Ping Wang
  • Patent number: 12278370
    Abstract: The present invention relates to a carbon nanotube-transition metal oxide composite and a method for making the composite. The composite comprises at least one carbon nanotube and a plurality of transition metal oxide nanoparticles. The plurality of transition metal oxide nanoparticles are chemically bonded to the at least one carbon nanotube through carbon-oxygen-metal (C—O-M) linkages, wherein the metal is a transition metal element. The method for making the composite comprising the following steps: step 1, providing at least one carbon nanotube obtained from a super-aligned carbon nanotube array; step 2, pre-oxidizing the at least one carbon nanotube; step 3, dispersing the at least one carbon nanotube in a solvent to form a first suspension; step 4, dispersing a material containing transition metal oxyacid radicals in the first suspension to form a second suspension; and step 5, removing the solvent from the second suspension and drying the second suspension.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: April 15, 2025
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Tao Wang, Li Sun, Ke Wang, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 12274180
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen