Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract: Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.

Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a semiconductor substrate including a cavity and a movable feature in the cavity. The semiconductor device structure also includes a cap substrate bonded to the semiconductor substrate to seal the cavity. There is an interface between the cap substrate and the semiconductor substrate. The semiconductor device structure further includes a sealing feature embedded in the semiconductor substrate and surrounding the cavity. The sealing feature extends across the interface and penetrates through the cap substrate.

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.

Abstract: A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.

Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.

Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

Abstract: An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold a top surface of the substrate stack, and at least one blade configured to be inserted between two adjacent substrates of the substrate stack, wherein the at least one blade has a pointed tip in plan view and has a channel configured to inject air or fluid.

Abstract: An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.

Abstract: A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section.

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Abstract: A bonding system includes: a storage apparatus, including a chamber, wherein the chamber is configured to accommodate a first semiconductor wafer and a second semiconductor wafer transferred from a load port, and a gas is provided to the chamber to purge oxygen out of the chamber; a surface treatment station, configured to perform a surface activation upon the first and second semiconductor wafers transferred from the storage apparatus; a cleaning station, configured to remove undesirable substances from surfaces of the first and second semiconductor wafers transferred from the surface treatment station; and a pre-bonding station, configured to bond the first and second semiconductor wafers together to produce a bonded first and second semiconductor wafer pair, wherein the first and second semiconductor wafers are transferred from the cleaning station. An associated apparatus and method are also disclosed.

Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Abstract: A semiconductor manufacturing method is disclosed. The method includes: providing a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded together; submerging the bonded first and second wafers in an ultrasonic transmitting medium; producing ultrasonic waves; and directing the ultrasonic waves to the bonded first and second wafers through the ultrasonic transmitting medium for a predetermined time period. An associated semiconductor manufacturing system for at least weakening a bonding strength of bonded wafers is also disclosed.