Patents by Inventor Rahul Agarwal

Rahul Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11388325
    Abstract: In some embodiments, apparatuses, systems, and methods are provided herein useful to assessing products. In some embodiments, an enclosure for use in assessing products comprises a housing including a door configured to allow placement of a product within the housing, a product holding surface located within the housing allowing pictures to be taken through the product holding surface and configured to support the product, a first image capture device configured to capture an image of the product from a first perspective, a second image capture device configured to capture an image of the product from a second perspective, and wherein the image of the product from the second perspective is captured through the product holding surface, and a lighting element, wherein the lighting element is located within the housing, and wherein the lighting element is configured to provide lighting within the housing.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 12, 2022
    Assignee: Walmart Apollo, LLC
    Inventors: Joshua T. Bohling, Chuck E. Tilmon, Emily Moneka Francis Xavier, Daniel J. Pumford, Brian J. A. Schardt, Issac Mathew, Venkataraja Nellore, Gaurav Savlani, Viraj C. Patel, Rahul Agarwal, Pushkar Pushp, Jennifer McTeer
  • Publication number: 20220206221
    Abstract: Manufacturing a semiconductor chip package with optical fiber attach capability includes preparing a photonic integrated circuit by etching a v-groove in a front side fiber coupling region; assembling the photonic integrated circuit on an organic redistribution layer; etching the organic redistribution layer; and attaching an optical fiber to the front side fiber coupling region.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: SIDDHARTH RAVICHANDRAN, BRETT P. WILKERSON, RAHUL AGARWAL
  • Publication number: 20220210314
    Abstract: In some embodiments, apparatuses, systems, and methods are provided herein useful to assessing products. In some embodiments, an enclosure for use in assessing products comprises a housing including a door configured to allow placement of a product within the housing, a product holding surface located within the housing allowing pictures to be taken through the product holding surface and configured to support the product, a first image capture device configured to capture an image of the product from a first perspective, a second image capture device configured to capture an image of the product from a second perspective, and wherein the image of the product from the second perspective is captured through the product holding surface, and a lighting element, wherein the lighting element is located within the housing, and wherein the lighting element is configured to provide lighting within the housing.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Inventors: Joshua T. Bohling, Chuck E. Tilmon, Emily Moneka Francis Xavier, Daniel J. Pumford, Brian J. A. Schardt, Issac Mathew, Venkataraja Nellore, Gaurav Savlani, Viraj C. Patel, Rahul Agarwal, Pushkar Pushp, Jennifer McTeer
  • Publication number: 20220208712
    Abstract: A method of manufacturing a semiconductor device, including: bonding a first chip layer comprising a first semiconductor chip to a second chip layer comprising a second semiconductor chip to electrically couple an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; and bonding a third chip layer comprising a third semiconductor chip to the second chip layer to electrically couple an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: RAHUL AGARWAL, RAJA SWAMINATHAN
  • Patent number: 11367628
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 21, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
  • Publication number: 20220189897
    Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Inventor: RAHUL AGARWAL
  • Publication number: 20220189987
    Abstract: A vertical channel of a three-dimensional (3D) NAND has a recessed and filled drain/source pocket region for each memory cell to reduce resistance in a region that traditionally has high resistance. The vertical channel conducts current whose resistivity is controlled through a series of memory cells. The vertical channel can have a polysilicon material to conduct current past the memory cell gates and drain/sources region between the memory elements. The recess can extend the polysilicon away from a center of the vertical channel and closer to the control gates. The recess includes a structure to reduce resistance in the drain/source region along the vertical channel between memory cell gates.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Henok T. MEBRAHTU, Rahul AGARWAL, Randy J. KOVAL, Guangyu HUANG
  • Publication number: 20220189879
    Abstract: A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: RAHUL AGARWAL, MILIND S. BHAGAVAT
  • Publication number: 20220147382
    Abstract: Disclosed are various embodiments for creating and managing virtual appliances. A command to create a virtual machine image for a hosted instance of an application image is received. The virtual machine image is created in response to receiving the command. The virtual machine image can include an operating system; a container orchestration service configured to host the instance of the application image; and a configuration service. The configuration service can be configured to at least install a management agent in response to a first boot of the virtual machine and configure the management agent to download and install the application image.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Steven Taylor, Rahul Agarwal, Etienne Robert Le Sueur, Sindhu Shashidhara, Sunny Tulsi Sreedhar Murthy, Gal Yardeni, Sandhya Pai
  • Publication number: 20220102276
    Abstract: A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: RAHUL AGARWAL, MILIND S. BHAGAVAT
  • Patent number: 11269676
    Abstract: Disclosed are various embodiments for creating and managing virtual appliances. A command to create a virtual machine image for a hosted instance of an application image is received. The virtual machine image is created in response to receiving the command. The virtual machine image can include an operating system; a container orchestration service configured to host the instance of the application image; and a configuration service. The configuration service can be configured to at least install a management agent in response to a first boot of the virtual machine and configure the management agent to download and install the application image.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 8, 2022
    Assignee: VMWARE, INC.
    Inventors: Steven Taylor, Rahul Agarwal, Etienne Robert Le Sueur, Sindhu Shashidhara, Sunny Tulsi Sreedhar Murthy, Gal Yardeni, Sandhya Pai
  • Publication number: 20220051989
    Abstract: A semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies. The interconnect structure implements a plurality of die-to-die connection pathways having a first density and a plurality of fan-out redistribution pathways having a second density that is different from the first density.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 17, 2022
    Inventors: RAHUL AGARWAL, BRETT P. WILKERSON, RAJA SWAMINATHAN
  • Publication number: 20220052023
    Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.
    Type: Application
    Filed: August 26, 2020
    Publication date: February 17, 2022
    Inventors: LEI FU, BRETT P. WILKERSON, RAHUL AGARWAL
  • Publication number: 20220051985
    Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 17, 2022
    Inventors: RAHUL AGARWAL, RAJA SWAMINATHAN, MICHAEL S. ALFANO, GABRIEL H. LOH, ALAN D. SMITH, GABRIEL WONG, MICHAEL MANTOR
  • Publication number: 20220046164
    Abstract: In some embodiments, apparatuses, systems, and methods are provided herein useful to assessing products. In some embodiments, an enclosure for use in assessing products comprises a housing including a door configured to allow placement of a product within the housing, a product holding surface located within the housing allowing pictures to be taken through the product holding surface and configured to support the product, a first image capture device configured to capture an image of the product from a first perspective, a second image capture device configured to capture an image of the product from a second perspective, and wherein the image of the product from the second perspective is captured through the product holding surface, and a lighting element, wherein the lighting element is located within the housing, and wherein the lighting element is configured to provide lighting within the housing.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 10, 2022
    Inventors: Joshua T. Bohling, Chuck E. Tilmon, Emily Moneka Francis Xavier, Daniel J. Pumford, Brian J.A. Schardt, Issac Mathew, Venkataraja Nellore, Gaurav Savlani, Viraj C. Patel, Rahul Agarwal, Pushkar Pushp, Jennifer McTeer
  • Publication number: 20220035689
    Abstract: A method of configuring a hybrid, multi-cloud gateway configuration system for executing an application programming interface (API) may comprise receiving, via a network interface device of the API service control plane system, gateway operation policies in a first format for execution of an API at a first gateway type and a second gateway type, generating via one of a plurality of gateway type policy translators and transmitting to a gateway of the first gateway type, a first configuration file in a second format, instructing the gateway of the first gateway type to provision the API to meet the gateway operation policies, and generating via another one of the plurality of gateway type policy translators and transmitting to a gateway of the second gateway type, a second configuration file in a third format, instructing the gateway of the second gateway type to provision the API to meet the gateway operation policies.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Applicant: BOOMI, INC.
    Inventors: Rajesh Raheja, Sean P. Collins, Rahul Agarwal, Ed Macosky
  • Publication number: 20220021803
    Abstract: A service verification system includes at least one collection truck including a hopper for receiving material and at least one camera positioned and oriented to image a container to be emptied into the hopper. At least one server receives images from the at least one camera. The collection truck may include an RFID reader configured to read RFID tags on containers to be emptied into the hopper. The server receives identification information from the RFID reader associated with the images from the camera. The images may be triggered upon the reading of the RFID tag, or by activation of a lift arm lifting the container, or manually by a driver.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 20, 2022
    Inventors: Jason Crawford Miller, Rahul Agarwal, Robert Lee Martin, JR.
  • Patent number: 11211332
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 28, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal
  • Patent number: 11197990
    Abstract: A system for supplying power transcutaneously to an implantable device implanted within a subject is provided. The system includes an external connector including one of a microneedle array and a microwire holder. The system further includes a power cable electrically coupled to the external connector and configured to supply power to the one of the microneedle array and the microwire holder, and an internal connector configured to be implanted within the subject and electrically coupled to the implantable device, the internal connector including the other of the microneedle array and the microwire holder. The microneedle array includes a plurality of electrically conductive microneedles, the microwire holder includes a plurality of electrical contacts, and the microwire holder is configured to engage the microneedle array such that the plurality of electrically conductive microneedles extend through the skin of the subject and electrically couple to the plurality of electrical contacts.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 14, 2021
    Assignee: TC1 LLC
    Inventors: Rahul Agarwal, Gene Bornzin, Edward Karst
  • Patent number: 11178389
    Abstract: A system is described for automatically calibrating a display device based at least on information relating to a user of the display device. The system obtains visual acuity information or pupillary information of the user. The system then determines a value of a display parameter of the display device based at least on the visual acuity information or the pupillary information of the user. The determined value is then provided for application to the display device. Other information may also be used in determining the value of the display parameter, such as user input, demographic information of the user, display device specific information, user environment information, displayed content information, or application context information. An algorithm may be used that determines the display parameter based on such information. The algorithm may comprise a model obtained through machine learning.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 16, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Praveen Sinha, Seema Lal Gulabrani, Ajay Vellanki, Rahul Agarwal, Arun Mudiraj