Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

Abstract: A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

Abstract: An electronic device includes a first integrated circuit die, a support structure, and a second integrated circuit die and may include a spacer. The support structure includes a circuit element. The support structure has a thickness of at least 110 microns. The spacer or second integrated circuit die includes a conductor. The spacer or second integrated circuit die is disposed between the first integrated circuit die and the support structure. The conductor is electrically coupled to the integrated circuit die or the circuit element of the support structure. The electronic device provides more flexibility to a designer by allowing a circuit element or circuit that occupies a significant area to be in the support structure.

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

Abstract: In an implementation, a semiconductor chip device includes a first semiconductor chip that includes a first portion and a second portion. The first portion can be a higher heat producing portion and the second portion can be a lower heat producing portion. A second semiconductor chip is stacked on the first semiconductor chip over the second portion. A dummy component is stacked on the first semiconductor chip over the first portion. The dummy component includes a plurality of thermal pipes providing a thermal path from a first surface of the dummy component to an opposite second surface of the dummy component.

Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

Abstract: An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

Abstract: A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).

Abstract: A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.

Abstract: Systems and methods are provided for authentication and authorizing a client device on a network. First, one or more packets are received from a computing entity indicating an authentication request from a client device requesting connection at a network. Next, identification information of the client device are extracted from a body of the packets. Credentials of the client device are verified based on the identification information. In response to verifying the credentials, a level of access of the client device at the network is determined. Based on the level of access, a VLAN is assigned to the client device. The systems concurrently transmit, in a single packet, to the computing entity, an indication of approval of the credentials and the assigned VLAN, wherein the computing entity provisions the assigned VLAN to the client device following an allocation of an IP address corresponding to the assigned VLAN to the client device.

Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: The present invention is generally related to methods and systems for preventing onset or worsening of RHF in patients with implanted ventricular assist devices. More particularly, the present invention relates to identifying patients at risk for RHF following implantation of a ventricular assist device based on pulmonary artery pressure measurement and/or trends and adjusting a pump operating parameter to prevent or reduce the onset or worsening of RHF in such patients, improve patient outcomes, or reduce mortality risks associated with VAD implantation. In particular, a pump operating parameter may be adjusted to reduce or minimize particularly high pressure loads on a patient’s heart or amount of time the patient is exposed to such high pressure loads following implantation.

Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.

Abstract: A chip for multi-die communications couplings using a single bridge die, includes: a plurality of dies each including one or more functional circuit blocks; and a first bridge die directly communicatively coupling two or more pairs of dies of the plurality of dies.

Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

Abstract: The present disclosure relates to a method of operating a database system. The database system comprises: a database; a first compute node comprising a first database proxy; and a second compute node comprising a second database proxy. The method comprises receiving and processing, at the first database proxy, a first plurality of access requests to access the database; receiving and processing, at the second database proxy, a second plurality of database access requests to access the database; monitoring for a failure event associated with the first database proxy; and, in response to the monitoring indicating a failure event, initiating a failover procedure between the first database proxy and the second database proxy. The failover procedure comprises: redirecting the first plurality of access requests to the second database proxy; and processing, at the second database proxy, the first plurality of access requests.

Abstract: A chip for controlled electrostatic discharging to avoid loading on input/output pins, comprising: a die comprising: a first plurality of connector pins each conductively coupled to one or more signal paths, each of the first plurality of connector pins having a first height; and a second plurality of connector pins independent of any signal paths, each of the second plurality of connector pins having a second height greater than the first height.