Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

Abstract: In various example embodiments, a vector modeling system is configured to access a set of data distributed across client devices and stored in a structured format. The vector modeling system determines vector parameters and vector templates suitable for the set of data and transforms the set of data from the structured format into a second format including one or more vectors based on one or more transformation strategies. The vector modeling system stores the transformed data and performs machine learning analysis on the vector.

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.

Abstract: Systems and methods for ranking search results based on members' posting activity and content are disclosed. The social networking system receives a search request for at least one member profile and retrieves member profiles in response to the search request. For a member profile in the member profiles, the social networking system identifies at least one submitted content item associated with the member profile and analyzes the at least one submitted content item to determine topics associated with the at least one submitted content item. The social networking system generates a topic similarity score for the member profile based on a comparison of the topics and a topic of interest associated with the search request. The social networking system ranks the member profiles based on generated topic similarity scores. The social networking system selects at least one member profile based on the member profile ranking.

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

Abstract: In an embodiment, a computer-implemented method comprises, in response to receiving lead data identifying an entity associated with a health care claim relating to suspected fraud, determining one or more data sources that were used to identify the entity or the suspected fraud; determining a subset of a plurality of data display elements, based on the determined one or more data sources, wherein each of the plurality of data display elements is configured to cause displaying health care claims data associated with the entity in a designated format; automatically obtaining, from a data repository, specific health care claims data associated with the entity for each of the plurality of data display elements in the subset; generating a lead summary report associated with the entity using a report template, the subset, and the obtained specific health care claims data.

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer structure that has plural conductor structures and plural glass interlevel dielectric layers. A glass encapsulant layer is positioned on the redistribution layer structure. A first semiconductor chip and a second semiconductor chip are positioned in the glass encapsulant layer and electrically connected by at least some of the conductor structures. A cap layer is on the encapsulant layer.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

Abstract: The system may validate a data source having a structured format and a grammar that includes tags. The system may identify a tag in the grammar. The system may parse the data source to extract attributes and/or values associated with the tags in response to successful validation. The system may also write the attributes and/or values to an output file separated by a preselected delimiter. A configuration file may identify the grammar, the preselected delimiter, and/or the data source. The data source may be in an XML format or a JSON format. The system may generate execution ready code in response to the validating the data source and the grammar. The output file may be a load ready file for ingestion into a big data storage format. The tag may include a parent tag and a sub tag corresponding to a hierarchy in the data source.

Abstract: The present invention is generally related to methods and systems for preventing onset or worsening of RHF in patients with implanted ventricular assist devices. More particularly, the present invention relates to identifying patients at risk for RHF following implantation of a ventricular assist device based on pulmonary artery pressure measurement and/or trends and adjusting a pump operating parameter to prevent or reduce the onset or worsening of RHF in such patients, improve patient outcomes, or reduce mortality risks associated with VAD implantation. In particular, a pump operating parameter may be adjusted to reduce or minimize particularly high pressure loads on a patient's heart or amount of time the patient is exposed to such high pressure loads following implantation.

Abstract: Controllers and methods for heart treatments are disclosed herein. The controller can include a communication module that can send and receive data from heart therapy devices. The controller can include memory including stored instruction. The controller can include a processor. The processor can receive a signal of an impending electrical treatment at a processor. The processor can determine a current operating parameter of a blood pump communicatingly coupled with the processor. The processor can determine an adjustment to the operating parameter of the blood pump to affect an impedance of heart tissue to be affected by the impending electrical treatment. The processor can control the blood pump according to the adjustment to the operating parameter of the blood pump.

Abstract: A system receives a source and a metadata layer that describes the source. The source may comprise source records with fields containing source data, and the metadata layer may include metadata comprising at least one of a field data type, a field data length, a field description, or a record length. The processor may further validate the metadata layer against the source and write results to a log. The processor may further be configured for transforming the source records into transformed records for a load ready file. The processor may further balance a number of records in the source against a number of transformed records in the load ready file to generate a transformation failure rate.

Abstract: In various example embodiments, a vector modeling system is configured to access a set of data distributed across client devices and stored in a structured format. The vector modeling system determines vector parameters and vector templates suitable for the set of data and transforms the set of data from the structured format into a second format including one or more vectors based on one or more transformation strategies. The vector modeling system stores the transformed data and performs machine learning analysis on the vector.

Abstract: In an embodiment, a computer-implemented method comprises, in response to receiving lead data identifying an entity associated with a health care claim relating to suspected fraud, determining one or more data sources that were used to identify the entity or the suspected fraud; determining a subset of a plurality of data display elements, based on the determined one or more data sources, wherein each of the plurality of data display elements is configured to cause displaying health care claims data associated with the entity in a designated format; automatically obtaining, from a data repository, specific health care claims data associated with the entity for each of the plurality of data display elements in the subset; generating a lead summary report associated with the entity using a report template, the subset, and the obtained specific health care claims data.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.