Patents by Inventor Rahul Agarwal

Rahul Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FAN-OUT PACKAGE WITH REINFORCING RIVETS
    Publication number: 20210057352
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 25, 2021
    Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
  • Die stacking for multi-tier 3D integration
    Patent number: 10930621
    Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: February 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat
  • SEMICONDUCTOR CHIP GETTERING
    Publication number: 20210050223
    Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: RAHUL AGARWAL, MILIND S. BHAGAVAT, IVOR BARBER, VENKATACHALAM VALLIAPPAN, YUEN TING CHENG, GUAN SIN CHOK
  • High density cross link die with polymer routing layer
    Patent number: 10923430
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: February 16, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Chun-Hung Lin, Rahul Agarwal, Milind Bhagavat, Fei Guo
  • MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES
    Publication number: 20210020459
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
  • METHODS, DEVICES AND SYSTEMS FOR HOLISTIC INTEGRATED HEALTHCARE PATIENT MANAGEMENT
    Publication number: 20210020294
    Abstract: A method for managing a treatment is provided. The method is under control of a processor. The method obtains a body generated analyte (BGA) indicative of a malnutrition state (MS) characteristic of interest (COI) of a patient and obtains implantable medical device (IMD) data indicative of a physiologic COI from the patient. The method assigns a health risk index based on the MS COI and the physiologic COI. The health risk index is indicative of a chronic disease state and malnutrition state currently exhibited by the patient. The method generates a treatment notification based on the health risk index.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 21, 2021
    Inventors: Rupinder Bharmi, Rahul Agarwal, Philip B. Adamson, Heidi Hellman, Nirav Dalal
  • MANAGED VIRTUAL APPLIANCES
    Publication number: 20210019163
    Abstract: Disclosed are various embodiments for creating and managing virtual appliances. A command to create a virtual machine image for a hosted instance of an application image is received. The virtual machine image is created in response to receiving the command. The virtual machine image can include an operating system; a container orchestration service configured to host the instance of the application image; and a configuration service. The configuration service can be configured to at least install a management agent in response to a first boot of the virtual machine and configure the management agent to download and install the application image.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Inventors: Steven Taylor, Rahul Agarwal, Etienne Robert Le Sueur, Sindhu Shashidhara, Sunny Tulsi Sreedhar Murthy, Gal Yardeni, Sandhya Pai
  • GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS
    Publication number: 20200409859
    Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Skyler J. SALEH, Samuel NAFFZIGER, Milind S. BHAGAVAT, Rahul AGARWAL
  • HIGH DENSITY CROSS LINK DIE WITH POLYMER ROUTING LAYER
    Publication number: 20200411443
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.
    Type: Application
    Filed: June 30, 2019
    Publication date: December 31, 2020
    Inventors: Fei Guo, Chun-Hung Lin, Rahul Agarwal, Milind Bhagavat
  • Model object management and storage system
    Patent number: 10866936
    Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: December 15, 2020
    Assignee: Palantir Technologies Inc.
    Inventors: David Lisuk, Daniel Erenrich, Guodong Xu, Luis Voloch, Rahul Agarwal, Simon Slowik, Aleksandr Zamoshchin, Andre Frederico Cavalheiro Menck, Anirvan Mukherjee, Daniel Chin
  • Integrated circuit module with integrated discrete devices
    Patent number: 10867978
    Abstract: In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 15, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Rahul Agarwal
  • Adjusting search results based on overlapping work histories
    Patent number: 10831846
    Abstract: Techniques for ranking search results generated by a search engine are described. A search query initiated by a searcher is processed to identify a set of member profiles satisfying the search query. A ranking score is assigned to each member profile of the set of member profiles. A subset of the set of member profiles is identified based on a determination of an overlap between a work history specified in each of the subset of member profiles and a work history specified in a profile of the searcher. The ranking score assigned to a member profile of the subset of the set of member profiles is adjusted based on the determination. A portion of each of the set of member profiles satisfying the search query is communicated for presentation as search results in a search results interface.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 10, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Rahul Agarwal
  • DIE STACKING FOR MULTI-TIER 3D INTEGRATION
    Publication number: 20200350292
    Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Rahul Agarwal, Milind S, Bhagavat
  • Semiconductor chip gettering
    Patent number: 10825692
    Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 3, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat, Ivor Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok
  • System and Method for Developing Voice Interactive Ecommerce Store
    Publication number: 20200342522
    Abstract: Systems and methods for easily creating and operating a voice-interactive shopping experience are disclosed. A merchant creates a voice store using a voice store creator platform. According to one process, an existing online store connects to the platform. The platform creates a voice-searchable catalog from data available on the existing online store. The platform enables the merchant to create a voice shopping experience using plain language instructions and without programming experience. Customers access the voice store with voice-enabled devices such as mobile phones or personal computing devices. The customer searches and shops using voice interaction.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Applicant: Blutag, Inc.
    Inventors: Rahul Agarwal, Shilp Agarwal
  • MULTI-CHIP PACKAGE WITH OFFSET 3D STRUCTURE
    Publication number: 20200343236
    Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Gabriel H. Loh
  • System and apparatus for generation of multiple automated ephemeral chat messages
    Patent number: 10798029
    Abstract: A computer-implement process generally pertains to ephemeral chat messaging, and in particular, maintaining context of a conversation between a BOT and a user from one webpage of a web browser to another webpage of the web browser. The computer-implemented process includes adding a message to a chat widget. The chat widget is displayed within the webpage of the web browser and the message being added is from the other webpage that the user responded to. The computer-implemented process also includes discarding one or more previous messages in the chat widget that are not responded to by the user, allowing the conversation between the BOT and the user to persist while retaining the context of the conversation from the other webpage.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: October 6, 2020
    Assignee: Freshworks, Inc.
    Inventors: Ajeet Singh Kushwaha, Rahul Agarwal, Rimaljit Kaur
  • SELF-CALIBRATING DISPLAY DEVICE
    Publication number: 20200314416
    Abstract: A system is described for automatically calibrating a display device based at least on information relating to a user of the display device. The system obtains visual acuity information or pupillary information of the user. The system then determines a value of a display parameter of the display device based at least on the visual acuity information or the pupillary information of the user. The determined value is then provided for application to the display device. Other information may also be used in determining the value of the display parameter, such as user input, demographic information of the user, display device specific information, user environment information, displayed content information, or application context information. An algorithm may be used that determines the display parameter based on such information. The algorithm may comprise a model obtained through machine learning.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Praveen Sinha, Seema Lal Gulabrani, Ajay Vellanki, Rahul Agarwal, Arun Mudiraj
  • INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR
    Publication number: 20200312766
    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
  • 3-dimensional flash memory with increased floating gate length
    Patent number: 10784274
    Abstract: An integrated circuit memory cell includes a floating gate, a control gate, and a plurality of inter-poly dielectric (IPD) layers. The IPD layers include an IPD1 layer, an IPD2 layer, and an IPD3 layer, with the IPD2 layer interposed between the IPD1 and IPD3 layers. The IPD2 layer, which may be a nitride, does not flank the floating gate. Thus, no section of the floating gate is laterally between two sections of the IPD2 layer. Also, no section of the IPD2 layer of a first memory cell is between the floating gate of the first memory cell and a floating gate of an immediate adjacent memory cell of the same memory cell string. In some cases, an IPD4 layer is provided between the floating gate and the IPD3 layer. The IPD4 layer is relatively much thinner than layers IPD1-3 and may flank the floating gate, as may the IPD3 layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Agarwal, Srivardhan Gowda, Krishna Parat