Patents by Inventor Rai-Min Huang
Rai-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130141Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: United Microelectronics Corp.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Publication number: 20240074209Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.Type: ApplicationFiled: November 2, 2023Publication date: February 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11895848Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: GrantFiled: May 22, 2022Date of Patent: February 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Patent number: 11849592Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.Type: GrantFiled: August 15, 2022Date of Patent: December 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11800723Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.Type: GrantFiled: September 13, 2020Date of Patent: October 24, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Fan Chang, Hung-Yueh Chen, Rai-Min Huang, Jia-Rong Wu, Yu-Ping Wang
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Publication number: 20230337551Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.Type: ApplicationFiled: May 13, 2022Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Chi-Hsuan Cheng, Rai-Min Huang, Po-Kai Hsu
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Publication number: 20230247915Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.Type: ApplicationFiled: April 11, 2023Publication date: August 3, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
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Publication number: 20230247914Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.Type: ApplicationFiled: April 11, 2023Publication date: August 3, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11665978Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.Type: GrantFiled: July 15, 2020Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11659772Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.Type: GrantFiled: March 28, 2022Date of Patent: May 23, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
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Publication number: 20230157182Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang, Yu-Ping Wang
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Publication number: 20220392954Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11456331Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.Type: GrantFiled: April 23, 2020Date of Patent: September 27, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
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Publication number: 20220285437Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: ApplicationFiled: May 22, 2022Publication date: September 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Publication number: 20220216397Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
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Patent number: 11374055Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.Type: GrantFiled: February 16, 2020Date of Patent: June 28, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Patent number: 11322682Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.Type: GrantFiled: January 19, 2021Date of Patent: May 3, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
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Publication number: 20220052110Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.Type: ApplicationFiled: September 13, 2020Publication date: February 17, 2022Inventors: I-Fan Chang, Hung-Yueh Chen, Rai-Min Huang, Jia-Rong Wu, Yu-Ping Wang
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Publication number: 20210391531Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.Type: ApplicationFiled: July 15, 2020Publication date: December 16, 2021Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
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Publication number: 20210305316Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.Type: ApplicationFiled: April 23, 2020Publication date: September 30, 2021Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang