Patents by Inventor Rai-Min Huang
Rai-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210225933Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.Type: ApplicationFiled: February 16, 2020Publication date: July 22, 2021Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
-
Publication number: 20210167282Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.Type: ApplicationFiled: January 19, 2021Publication date: June 3, 2021Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
-
Publication number: 20210151664Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.Type: ApplicationFiled: December 4, 2019Publication date: May 20, 2021Inventors: Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang, Yu-Ping Wang
-
Publication number: 20210135092Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.Type: ApplicationFiled: November 27, 2019Publication date: May 6, 2021Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Hung-Yueh Chen, Yu-Ping Wang, Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang
-
Patent number: 10944048Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.Type: GrantFiled: August 28, 2019Date of Patent: March 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Tsai, Rai-Min Huang
-
Patent number: 10937946Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.Type: GrantFiled: August 15, 2019Date of Patent: March 2, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
-
Patent number: 10930704Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.Type: GrantFiled: March 8, 2020Date of Patent: February 23, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
-
Publication number: 20210028353Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.Type: ApplicationFiled: August 28, 2019Publication date: January 28, 2021Inventors: Ya-Huei Tsai, Rai-Min Huang
-
Publication number: 20210020694Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.Type: ApplicationFiled: March 8, 2020Publication date: January 21, 2021Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
-
Publication number: 20210013396Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.Type: ApplicationFiled: August 15, 2019Publication date: January 14, 2021Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
-
Patent number: 10714466Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.Type: GrantFiled: January 23, 2019Date of Patent: July 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
-
Publication number: 20200212030Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.Type: ApplicationFiled: January 23, 2019Publication date: July 2, 2020Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
-
Patent number: 10622407Abstract: A magnetic memory cell includes a substrate having a memory region, a transistor within the memory region, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a cylindrical memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The cylindrical memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane is lower than the first horizontal plane.Type: GrantFiled: August 20, 2019Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
-
Patent number: 10090398Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.Type: GrantFiled: July 12, 2017Date of Patent: October 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
-
Patent number: 9859402Abstract: The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively. An etching process is then performed to form a plurality of trenches in the first dielectric layer, and a conductive layer is filled in each trench to form a plurality of contacts in the first dielectric layer.Type: GrantFiled: March 16, 2015Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Rai-Min Huang
-
Patent number: 9859147Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.Type: GrantFiled: October 28, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
-
Publication number: 20170309727Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
-
Patent number: 9786502Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.Type: GrantFiled: March 10, 2016Date of Patent: October 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Hsien Li, Rai-Min Huang, I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
-
Publication number: 20170263454Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.Type: ApplicationFiled: March 10, 2016Publication date: September 14, 2017Inventors: Kuan-Hsien Li, Rai-Min Huang, I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
-
Patent number: 9755048Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.Type: GrantFiled: May 13, 2015Date of Patent: September 5, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li